Add STM32F042F6 (#86)

* Add STM32F042F6

* Add a newline to the end of Makefile

* Fix the interrupt driven example

Makefile

@@ -259,3 +259,9 @@ stm32f745xe_hs: clean
 						LDSCRIPT='demo/stm32f745xe.ld' \
 						DEFINES='STM32F7 STM32F745xx USBD_SOF_DISABLED USBD_PRIMARY_OTGHS' \
 						CFLAGS='-mcpu=cortex-m7'
+
+stm32f042f6: clean
+	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F0xx/Source/Templates/gcc/startup_stm32f042x6.s' \
+						LDSCRIPT='demo/stm32f042x6.ld' \
+						DEFINES='STM32F0 STM32F042x6 USBD_SOF_DISABLED' \
+						CFLAGS='-mcpu=cortex-m0 -DUSBD_PINS_REMAP'

demo/cdc_loop.c

@@ -470,8 +470,9 @@ static void cdc_init_usbd(void) {
 }
 
 #if defined(CDC_USE_IRQ)
-#if defined(STM32L052xx) || defined(STM32F070xB)
-    #define USB_HANDLER     USB_IRQHandler
+#if defined(STM32L052xx) || defined(STM32F070xB) || \
+	defined(STM32F042x6)
+#define USB_HANDLER     USB_IRQHandler
     #define USB_NVIC_IRQ    USB_IRQn
 #elif defined(STM32L100xC) || defined(STM32G4)
     #define USB_HANDLER     USB_LP_IRQHandler

demo/cdc_startup.c

@@ -242,6 +242,12 @@ static void cdc_init_rcc (void) {
     _BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
     _WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL);
     _BST(RCC->CFGR3, RCC_CFGR3_USBSW_PLLCLK);
+#elif defined(STM32F042x6)
+    /* set flash latency 1WS */
+    _BST(FLASH->ACR, FLASH_ACR_LATENCY);
+    /* use HSI48 as clock incl. USB PHY clock, no PLL */
+	_BST(RCC->CR2, RCC_CR2_HSI48ON);
+	_WBS(RCC->CR2, RCC_CR2_HSI48RDY);
 #elif defined(STM32G4)
     /* using HSI16 as AHB/CPU clock, HSI48 as USB PHY clock */
     _BST(RCC->CRRCR, RCC_CRRCR_HSI48ON);

demo/stm32f042x6.ld

@@ -0,0 +1,8 @@
+ENTRY(Reset_Handler)
+MEMORY
+{
+    ROM  (rx): ORIGIN = 0x08000000, LENGTH =  32K
+    RAM (rwx): ORIGIN = 0x20000000, LENGTH =  6K
+}
+
+INCLUDE sections.ld