add F405 demo

Makefile

@@ -228,4 +228,16 @@ stm32l053x8 32l053r8-nucleo: clean
 	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l053xx.s' \
 						LDSCRIPT='demo/stm32l052x8.ld' \
 						DEFINES='STM32L0 STM32L053xx USBD_SOF_DISABLED' \
-						CFLAGS='-mcpu=cortex-m0plus'
+						CFLAGS='-mcpu=cortex-m0plus'
+
+stm32f405xg: clean
+	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s' \
+						LDSCRIPT='demo/stm32f405xg.ld' \
+						DEFINES='STM32F4 STM32F405xx USBD_SOF_DISABLED' \
+						CFLAGS='-mcpu=cortex-m4'
+
+stm32f405xg_hs: clean
+	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s' \
+						LDSCRIPT='demo/stm32f405xg.ld' \
+						DEFINES='STM32F4 STM32F405xx USBD_SOF_DISABLED USBD_PRIMARY_OTGHS' \
+						CFLAGS='-mcpu=cortex-m4'

demo/cdc_startup.c

@@ -113,7 +113,7 @@ static void cdc_init_rcc (void) {
     _BMD(GPIOA->MODER, (0x03 << 22) | (0x03 << 24), (0x02 << 22) | (0x02 << 24)); // MCO
 
 
-#elif defined(STM32F429xx)
+#elif defined(STM32F429xx) || defined(STM32F405xx)
     /* set flash latency 2WS */
     _BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_2WS);
     /* setting up PLL 16MHz HSI, VCO=144MHz, PLLP = 72MHz PLLQ = 48MHz  */

demo/stm32f405xg.ld

@@ -0,0 +1,9 @@
+ENTRY(Reset_Handler)
+MEMORY
+{
+	ROM    (rx): ORIGIN = 0x08000000, LENGTH = 1024K
+	RAM   (rwx): ORIGIN = 0x20000000, LENGTH = 128K
+	RAM2  (rwx): ORIGIN = 0x10000000, LENGTH = 64K
+}
+
+INCLUDE sections.ld