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@@ -0,0 +1,458 @@
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+#include <stdint.h>
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+#include <stdbool.h>
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+#include "macro.h"
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+#include "stm32.h"
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+#include "../usb.h"
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+
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+#if defined(USE_STMV2_DRIVER)
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+
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+#define VBUS_DETECTION 0
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+
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+#define MAX_EP 6
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+#define MAX_RX_PACKET 128
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+#define MAX_CONTROL_EP 1
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+#define MAX_FIFO_SZ 320 /*in 32-bit chunks */
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+
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+#define RX_FIFO_SZ ((4 * MAX_CONTROL_EP + 6) + ((MAX_RX_PACKET / 4) + 1) + (MAX_EP * 2) + 1)
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+
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+USB_OTG_GlobalTypeDef * const OTG = (void*)(USB_OTG_FS_PERIPH_BASE + USB_OTG_GLOBAL_BASE);
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+USB_OTG_DeviceTypeDef * const OTGD = (void*)(USB_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE);
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+volatile uint32_t * const OTGPCTL = (void*)(USB_OTG_FS_PERIPH_BASE + USB_OTG_PCGCCTL_BASE);
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+
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+
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+inline static volatile uint32_t* EPFIFO(uint8_t ep) {
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+ return (uint32_t*)(USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (ep << 12));
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+}
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+
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+inline static USB_OTG_INEndpointTypeDef* EPIN(uint8_t ep) {
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+ return (void*)(USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE + (ep << 5));
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+}
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+
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+inline static USB_OTG_OUTEndpointTypeDef* EPOUT(uint8_t ep) {
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+ return (void*)(USB_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE + (ep << 5));
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+}
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+
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+inline static void Flush_RX(void) {
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+ _BST(OTG->GRSTCTL, USB_OTG_GRSTCTL_RXFFLSH);
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+ _WBC(OTG->GRSTCTL, USB_OTG_GRSTCTL_RXFFLSH);
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+}
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+
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+inline static void Flush_TX(uint8_t ep) {
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+ _BMD(OTG->GRSTCTL, USB_OTG_GRSTCTL_TXFNUM,
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+ _VAL2FLD(USB_OTG_GRSTCTL_TXFNUM, ep) | USB_OTG_GRSTCTL_TXFFLSH);
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+ _WBC(OTG->GRSTCTL, USB_OTG_GRSTCTL_TXFFLSH);
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+}
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+
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+void ep_setstall(uint8_t ep, bool stall) {
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+ if (ep & 0x80) {
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+ ep &= 0x7F;
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+ uint32_t _t = EPIN(ep)->DIEPCTL;
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+ if (_t & USB_OTG_DIEPCTL_USBAEP) {
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+ if (stall) {
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+ _BST(_t, USB_OTG_DIEPCTL_STALL);
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+ } else {
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+ _BMD(_t, USB_OTG_DIEPCTL_STALL,
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+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_SNAK);
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+ }
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+ EPIN(ep)->DIEPCTL = _t;
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+ }
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+ } else {
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+ uint32_t _t = EPOUT(ep)->DOEPCTL;
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+ if (_t & USB_OTG_DOEPCTL_USBAEP) {
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+ if (stall) {
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+ _BST(_t, USB_OTG_DOEPCTL_STALL);
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+ } else {
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+ _BMD(_t, USB_OTG_DOEPCTL_STALL,
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+ USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_CNAK);
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+ }
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+ EPOUT(ep)->DOEPCTL = _t;
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+ }
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+ }
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+}
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+
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+bool ep_isstalled(uint8_t ep) {
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+ if (ep & 0x80) {
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+ ep &= 0x7F;
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+ return (EPIN(ep)->DIEPCTL & USB_OTG_DIEPCTL_STALL) ? true : false;
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+ } else {
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+ return (EPOUT(ep)->DOEPCTL & USB_OTG_DOEPCTL_STALL) ? true : false;
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+ }
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+}
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+
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+void enable(bool enable) {
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+ if (enable) {
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+ /* enabling USB_OTG in RCC */
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+ _BST(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
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+ /* Set Vbus enabled for USB */
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+ _BST(PWR->CR2, PWR_CR2_USV);
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+ /* select Internal PHY */
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+ OTG->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
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+ /* do core soft reset */
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+ _WBS(OTG->GRSTCTL, USB_OTG_GRSTCTL_AHBIDL);
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+ _BST(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
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+ _WBC(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
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+ /* configure OTG as device */
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+ OTG->GUSBCFG = USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL |
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+ _VAL2FLD(USB_OTG_GUSBCFG_TRDT, 0x06);
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+ /* configuring Vbus sense and powerup PHY */
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+#if (VBUS_DETECTION)
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+ OTG->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_PWRDWN;
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+#else
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+ OTG->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
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+ OTG->GCCFG = USB_OTG_GCCFG_PWRDWN;
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+#endif
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+ /* restart PHY*/
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+ *OTGPCTL = 0;
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+ /* soft disconnect device */
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+ _BST(OTGD->DCTL, USB_OTG_DCTL_SDIS);
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+ /* Setup USB FS speed and frame interval */
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+ _BMD(OTGD->DCFG, USB_OTG_DCFG_PERSCHIVL | USB_OTG_DCFG_DSPD,
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+ _VAL2FLD(USB_OTG_DCFG_PERSCHIVL, 0) | _VAL2FLD(USB_OTG_DCFG_DSPD, 0x03));
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+ /* unmask EP interrupts */
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+ OTGD->DIEPMSK = USB_OTG_DIEPMSK_XFRCM;
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+ /* unmask core interrupts */
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+ OTG->GINTMSK = USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM |
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+ USB_OTG_GINTMSK_SOFM |
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+ USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM |
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+ USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_RXFLVLM;
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+ /* clear pending interrupts */
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+ OTG->GINTSTS = 0xFFFFFFFF;
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+ /* unmask global interrupt */
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+ OTG->GAHBCFG = USB_OTG_GAHBCFG_GINT;
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+ /* setting max RX FIFO size */
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+ OTG->GRXFSIZ = RX_FIFO_SZ;
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+ /* setting up EP0 TX FIFO SZ as 64 byte */
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+ OTG->GNPTXFSIZ = RX_FIFO_SZ | (0x10 << 16);
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+ } else {
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+ if (RCC->AHB2ENR & RCC_AHB2ENR_OTGFSEN) {
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+ _BCL(PWR->CR2, PWR_CR2_USV);
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+ _BST(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST);
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+ _BCL(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST);
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+ _BCL(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
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+ }
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+ }
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+}
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+
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+void reset (void) {
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+ // _BST(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
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+ // _WBC(OTG->GRSTCTL, USB_OTG_GRSTCTL_CSRST);
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+}
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+
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+
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+void connect(bool connect) {
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+ if (connect) {
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+ _BCL(OTGD->DCTL, USB_OTG_DCTL_SDIS);
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+ } else {
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+ _BST(OTGD->DCTL, USB_OTG_DCTL_SDIS);
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+ }
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+}
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+
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+void setaddr (uint8_t addr) {
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+ _BMD(OTGD->DCFG, USB_OTG_DCFG_DAD, addr << 4);
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+}
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+
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+/**\brief Helper. Set up TX fifo
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+ * \param ep endpoint index
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+ * \param epsize required max packet size in bytes
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+ * \return true if TX fifo is successfully set
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+ */
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+static bool set_tx_fifo(uint8_t ep, uint16_t epsize) {
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+ uint32_t _fsa = OTG->GNPTXFSIZ;
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+ /* calculating initial TX FIFO address. next from EP0 TX fifo */
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+ _fsa = 0xFFFF & (_fsa + (_fsa >> 16));
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+ /* looking for next free TX fifo address */
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+ for (int i = 0; i < (MAX_EP - 1); i++) {
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+ uint32_t _t = OTG->DIEPTXF[i];
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+ if ((_t & 0xFFFF) < 0x200) {
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+ _t = 0xFFFF & (_t + (_t >> 16));
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+ if (_t > _fsa) {
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+ _fsa = _t;
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+ }
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+ }
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+ }
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+ /* calculating requited TX fifo size */
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+ /* getting in 32 bit terms */
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+ epsize = (epsize + 0x03) >> 2;
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+ /* it must be 16 32-bit words minimum */
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+ if (epsize < 0x10) epsize = 0x10;
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+ /* checking for the available fifo */
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+ if ((_fsa + epsize) > MAX_FIFO_SZ) return false;
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+ /* programming fifo register */
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+ _fsa |= (epsize << 16);
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+ OTG->DIEPTXF[ep - 1] = _fsa;
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+ return true;
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+}
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+
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+bool ep_config(uint8_t ep, uint8_t eptype, uint16_t epsize) {
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+ if (ep == 0) {
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+ /* configureing control endpoint EP0 */
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+ uint32_t mpsize;
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+ if (epsize <= 0x08) {
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+ epsize = 0x08;
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+ mpsize = 0x03;
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+ } else if (epsize <= 0x10) {
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+ epsize = 0x10;
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+ mpsize = 0x02;
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+ } else if (epsize <= 0x20) {
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+ epsize = 0x20;
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+ mpsize = 0x01;
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+ } else {
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+ epsize = 0x40;
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+ mpsize = 0x00;
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+ }
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+ /* EP0 TX FIFO size is setted on init level */
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+ /* enabling RX and TX interrupts from EP0 */
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+ OTGD->DAINTMSK |= 0x00010001;
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+ /* setting up EP0 TX and RX registers */
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+ /*EPIN(ep)->DIEPTSIZ = epsize;*/
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+ EPIN(ep)->DIEPCTL = mpsize | USB_OTG_DIEPCTL_SNAK;
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+ /* 1 setup packet, 1 packets total */
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+ EPOUT(ep)->DOEPTSIZ = epsize | (1 << 29) | (1 << 19);
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+ EPOUT(ep)->DOEPCTL = mpsize | USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
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+ return true;
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+ }
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+ if (ep & 0x80) {
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+ ep &= 0x7F;
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+ USB_OTG_INEndpointTypeDef* epi = EPIN(ep);
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+ /* configuring TX endpoint */
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+ /* setting up TX fifo and size register */
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+ if ((eptype == USB_EPTYPE_ISOCHRONUS) ||
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+ (eptype == (USB_EPTYPE_BULK | USB_EPTYPE_DBLBUF))) {
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+ if (!set_tx_fifo(ep, epsize << 1)) return false;
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+ } else {
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+ if (!set_tx_fifo(ep, epsize)) return false;
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+ }
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+ /* enabling EP TX interrupt */
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+ OTGD->DAINTMSK |= (0x0001UL << ep);
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+ /* setting up TX control register*/
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+ switch (eptype) {
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+ case USB_EPTYPE_ISOCHRONUS:
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+ epi->DIEPCTL = USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK |
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+ (0x01 << 18) | USB_OTG_DIEPCTL_USBAEP |
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+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
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+ (ep << 22) | epsize;
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+ break;
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+ case USB_EPTYPE_BULK:
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+ case USB_EPTYPE_BULK | USB_EPTYPE_DBLBUF:
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+ epi->DIEPCTL = USB_OTG_DIEPCTL_SNAK | USB_OTG_DIEPCTL_USBAEP |
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+ (0x02 << 18) | USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
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+ (ep << 22) | epsize;
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+ break;
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+ default:
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+ epi->DIEPCTL = USB_OTG_DIEPCTL_SNAK | USB_OTG_DIEPCTL_USBAEP |
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+ (0x03 << 18) | USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
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+ (ep << 22) | epsize;
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+ break;
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+ }
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+ } else {
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+ /* configuring RX endpoint */
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+ USB_OTG_OUTEndpointTypeDef* epo = EPOUT(ep);
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+ /* setting up RX control register */
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+ switch (eptype) {
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+ case USB_EPTYPE_ISOCHRONUS:
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+ epo->DOEPCTL = USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_CNAK |
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+ USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP |
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+ (0x01 << 18) | epsize;
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+ break;
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+ case USB_EPTYPE_BULK | USB_EPTYPE_DBLBUF:
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+ case USB_EPTYPE_BULK:
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+ epo->DOEPCTL = USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_CNAK |
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+ USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP |
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+ (0x02 << 18) | epsize;
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+ break;
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+ default:
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+ epo->DOEPCTL = USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_CNAK |
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+ USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP |
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+ (0x03 << 18) | epsize;
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+ break;
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+ }
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+ }
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+ return true;
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+}
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+
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+void ep_deconfig(uint8_t ep) {
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+ ep &= 0x7F;
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+ volatile USB_OTG_INEndpointTypeDef* epi = EPIN(ep);
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+ volatile USB_OTG_OUTEndpointTypeDef* epo = EPOUT(ep);
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+ /* deconfiguring TX part */
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+ /* disable interrupt */
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+ OTGD->DAINTMSK &= ~(0x10001 << ep);
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+ /* decativating endpoint */
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+ _BCL(epi->DIEPCTL, USB_OTG_DIEPCTL_USBAEP);
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+ /* flushing FIFO */
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+ Flush_TX(ep);
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+ /* disabling endpoint */
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+ if ((epi->DIEPCTL & USB_OTG_DIEPCTL_EPENA) && (ep != 0)) {
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+ epi->DIEPCTL = USB_OTG_DIEPCTL_EPDIS;
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+ _WBS(epi->DIEPINT, USB_OTG_DIEPINT_EPDISD);
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+ }
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+ /* clean EP interrupts */
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+ epi->DIEPINT = 0xFF;
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+ /* deconfiguring TX FIFO */
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+ if (ep > 0) {
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+ OTG->DIEPTXF[ep-1] = 0x02000200 + 0x200 * ep;
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+ }
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+ /* deconfigureing RX part */
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+ _BCL(epo->DOEPCTL, USB_OTG_DOEPCTL_USBAEP);
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+ if ((epo->DOEPCTL & USB_OTG_DOEPCTL_EPENA) && (ep != 0)) {
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+ epo->DOEPCTL = USB_OTG_DOEPCTL_EPDIS;
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+ _WBS(epo->DOEPINT, USB_OTG_DOEPINT_EPDISD);
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+ }
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+ epo->DOEPINT = 0xFF;
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+}
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+
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+int32_t ep_read(uint8_t ep, void* buf, uint16_t blen) {
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+ uint32_t len;
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+ volatile uint32_t *fifo = EPFIFO(0);
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+ USB_OTG_OUTEndpointTypeDef* epo = EPOUT(ep);
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+ /* no data in RX FIFO */
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+ if (!(OTG->GINTSTS & USB_OTG_GINTSTS_RXFLVL)) return -1;
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+ ep &= 0x7F;
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+ if ((OTG->GRXSTSR & USB_OTG_GRXSTSP_EPNUM) != ep) return -1;
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+ /* pop data from fifo */
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+ len = _FLD2VAL(USB_OTG_GRXSTSP_BCNT, OTG->GRXSTSP);
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+ for (int i = 0; i < len; i +=4) {
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+ uint32_t _t = *fifo;
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+ if (blen >= 4) {
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+ *(__attribute__((packed))uint32_t*)buf = _t;
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+ blen -= 4;
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+ buf += 4;
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+ } else {
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+ while (blen){
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+ *(uint8_t*)buf = 0xFF & _t;
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+ _t >>= 8;
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+ blen --;
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+ }
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+ }
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+ }
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+ _BST(epo->DOEPCTL, USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
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+ return len;
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+}
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+
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+int32_t ep_write(uint8_t ep, void *buf, uint16_t blen) {
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+ ep &= 0x7F;
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|
|
+ volatile uint32_t* _fifo = EPFIFO(ep);
|
|
|
+ USB_OTG_INEndpointTypeDef* epi = EPIN(ep);
|
|
|
+ /* transfer data size in 32-bit words */
|
|
|
+ uint32_t _len = (blen + 3) >> 2;
|
|
|
+ /* no enough space in TX fifo */
|
|
|
+ if (_len > epi->DTXFSTS) return -1;
|
|
|
+ if (ep != 0 && epi->DIEPCTL & USB_OTG_DIEPCTL_EPENA) {
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+ epi->DIEPTSIZ = 0;
|
|
|
+ epi->DIEPTSIZ = (1 << 19) + blen;
|
|
|
+ _BMD(epi->DIEPCTL, USB_OTG_DIEPCTL_STALL, USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK);
|
|
|
+ while (_len--) {
|
|
|
+ *_fifo = *(__attribute__((packed)) uint32_t*)buf;
|
|
|
+ buf += 4;
|
|
|
+ }
|
|
|
+ return blen;
|
|
|
+}
|
|
|
+
|
|
|
+uint16_t get_frame (void) {
|
|
|
+ return _FLD2VAL(USB_OTG_DSTS_FNSOF, OTGD->DSTS);
|
|
|
+}
|
|
|
+
|
|
|
+void evt_poll(usbd_device *dev, usbd_evt_callback callback) {
|
|
|
+ uint32_t evt;
|
|
|
+ uint32_t ep = 0;
|
|
|
+ while (1) {
|
|
|
+ uint32_t _t = OTG->GINTSTS;
|
|
|
+ /* bus RESET event */
|
|
|
+ if (_t & USB_OTG_GINTSTS_USBRST) {
|
|
|
+ OTG->GINTSTS = USB_OTG_GINTSTS_USBRST;
|
|
|
+ for (uint8_t i = 0; i < MAX_EP; i++ ) {
|
|
|
+ ep_deconfig(i);
|
|
|
+ }
|
|
|
+ Flush_RX();
|
|
|
+ continue;
|
|
|
+ } else if (_t & USB_OTG_GINTSTS_ENUMDNE) {
|
|
|
+ OTG->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
|
|
|
+ evt = usbd_evt_reset;
|
|
|
+ } else if (_t & USB_OTG_GINTSTS_IEPINT) {
|
|
|
+ for (;; ep++) {
|
|
|
+ USB_OTG_INEndpointTypeDef* epi = EPIN(ep);
|
|
|
+ if (ep >= MAX_EP) return;
|
|
|
+ if (epi->DIEPINT & USB_OTG_DIEPINT_XFRC) {
|
|
|
+ epi->DIEPINT = USB_OTG_DIEPINT_XFRC;
|
|
|
+ evt = usbd_evt_eptx;
|
|
|
+ ep |= 0x80;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ } else if (_t & USB_OTG_GINTSTS_RXFLVL) {
|
|
|
+ _t = OTG->GRXSTSR;
|
|
|
+ ep = _t & USB_OTG_GRXSTSP_EPNUM;
|
|
|
+ switch (_FLD2VAL(USB_OTG_GRXSTSP_PKTSTS, _t)) {
|
|
|
+ case 0x02:
|
|
|
+ evt = usbd_evt_eprx;
|
|
|
+ break;
|
|
|
+ case 0x06:
|
|
|
+ evt = usbd_evt_epsetup;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ OTG->GRXSTSP;
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ } else if (_t & USB_OTG_GINTSTS_SOF) {
|
|
|
+ OTG->GINTSTS = USB_OTG_GINTSTS_SOF;
|
|
|
+ evt = usbd_evt_sof;
|
|
|
+ } else if (_t & USB_OTG_GINTSTS_USBSUSP) {
|
|
|
+ evt = usbd_evt_susp;
|
|
|
+ OTG->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
|
|
|
+ } else if (_t & USB_OTG_GINTSTS_WKUINT) {
|
|
|
+ OTG->GINTSTS = USB_OTG_GINTSTS_WKUINT;
|
|
|
+ evt = usbd_evt_wkup;
|
|
|
+ } else {
|
|
|
+ /* no more supported events */
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ return callback(dev, evt, ep);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static uint32_t fnv1a32_turn (uint32_t fnv, uint32_t data ) {
|
|
|
+ for (int i = 0; i < 4 ; i++) {
|
|
|
+ fnv ^= (data & 0xFF);
|
|
|
+ fnv *= 16777619;
|
|
|
+ data >>= 8;
|
|
|
+ }
|
|
|
+ return fnv;
|
|
|
+}
|
|
|
+
|
|
|
+uint16_t get_serialno_desc(void *buffer) {
|
|
|
+ struct usb_string_descriptor *dsc = buffer;
|
|
|
+ uint16_t *str = dsc->wString;
|
|
|
+ uint32_t fnv = 2166136261;
|
|
|
+ fnv = fnv1a32_turn(fnv, *(uint32_t*)(UID_BASE + 0x00));
|
|
|
+ fnv = fnv1a32_turn(fnv, *(uint32_t*)(UID_BASE + 0x04));
|
|
|
+ fnv = fnv1a32_turn(fnv, *(uint32_t*)(UID_BASE + 0x14));
|
|
|
+ for (int i = 28; i >= 0; i -= 4 ) {
|
|
|
+ uint16_t c = (fnv >> i) & 0x0F;
|
|
|
+ c += (c < 10) ? '0' : ('A' - 10);
|
|
|
+ *str++ = c;
|
|
|
+ }
|
|
|
+ dsc->bDescriptorType = USB_DTYPE_STRING;
|
|
|
+ dsc->bLength = 18;
|
|
|
+ return 18;
|
|
|
+}
|
|
|
+
|
|
|
+const struct usbd_driver usb_stmv2 = {
|
|
|
+ USBD_HW_ADDRFST,
|
|
|
+ enable,
|
|
|
+ reset,
|
|
|
+ connect,
|
|
|
+ setaddr,
|
|
|
+ ep_config,
|
|
|
+ ep_deconfig,
|
|
|
+ ep_read,
|
|
|
+ ep_write,
|
|
|
+ ep_setstall,
|
|
|
+ ep_isstalled,
|
|
|
+ evt_poll,
|
|
|
+ get_frame,
|
|
|
+ get_serialno_desc,
|
|
|
+};
|
|
|
+
|
|
|
+#endif //USE_STM32V2_DRIVER
|
