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@@ -49,7 +49,7 @@ static void cdc_init_rcc (void) {
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_BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
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_WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL);
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-#elif defined(STM32L4)
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+#elif defined(STM32L476xx)
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_BST(RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
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/* Set power Range 1 */
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_BMD(PWR->CR1, PWR_CR1_VOS, PWR_CR1_VOS_0);
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@@ -167,6 +167,23 @@ static void cdc_init_rcc (void) {
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/* switch to PLL */
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_BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
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_WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL);
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+#elif defined(STM32L433xx)
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+ /* using HSI16 as AHB/CPU clock, HSI48 as USB PHY clock */
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+ _BST(RCC->CR, RCC_CR_HSION);
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+ _WBS(RCC->CR, RCC_CR_HSIRDY);
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+ _BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_HSI);
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+ _WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_HSI);
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+ _BST(RCC->CRRCR, RCC_CRRCR_HSI48ON);
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+ _WBS(RCC->CRRCR, RCC_CRRCR_HSI48RDY);
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+ _BMD(RCC->CCIPR, RCC_CCIPR_CLK48SEL, 0);
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+ /* setup PA11 PA12 to AF10 (USB FS) */
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+ _BST(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN);
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+ _BST(GPIOA->AFR[1], (0x0A << 12) | (0x0A << 16));
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+ _BMD(GPIOA->MODER, (0x03 << 22) | (0x03 << 24), (0x02 << 22) | (0x02 << 24));
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+ /* Disabling USB Vddusb power isolation. Vusb connected to Vdd */
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+ _BST(RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
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+ _BST(PWR->CR2, PWR_CR2_USV);
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+
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#else
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#error Not supported
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#endif
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