add STM32G4 series

Makefile

@@ -190,3 +190,9 @@ stm32f070xb: clean
 						LDSCRIPT='demo/stm32f070xb.ld' \
 						DEFINES='STM32F0 STM32F070xB USBD_SOF_DISABLED' \
 						CFLAGS='-mcpu=cortex-m0'
+
+stm32g431xb 32g431rb-nucleo: clean
+	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s' \
+						LDSCRIPT='demo/stm32g431xb.ld' \
+						DEFINES='STM32G4 STM32G431xx USBD_SOF_DISABLED' \
+						CFLAGS='-mcpu=cortex-m4'

demo/cdc_loop.c

@@ -462,7 +462,7 @@ static void cdc_init_usbd(void) {
 #if defined(STM32L052xx) || defined(STM32F070xB)
     #define USB_HANDLER     USB_IRQHandler
     #define USB_NVIC_IRQ    USB_IRQn
-#elif defined(STM32L100xC)
+#elif defined(STM32L100xC) || defined(STM32G4)
     #define USB_HANDLER     USB_LP_IRQHandler
     #define USB_NVIC_IRQ    USB_LP_IRQn
 #elif defined(STM32L476xx)

demo/cdc_startup.c

@@ -196,6 +196,10 @@ static void cdc_init_rcc (void) {
     _BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
     _WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL);
     _BST(RCC->CFGR3, RCC_CFGR3_USBSW_PLLCLK);
+#elif defined(STM32G4)
+    /* using HSI16 as AHB/CPU clock, HSI48 as USB PHY clock */
+    _BST(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+    _WBS(RCC->CRRCR, RCC_CRRCR_HSI48RDY);
 #else
     #error Not supported
 #endif

demo/stm32g431xb.ld

@@ -0,0 +1,88 @@
+ENTRY(Reset_Handler)
+MEMORY
+{
+    ROM   (rx): ORIGIN = 0x08000000, LENGTH = 128K
+    RAM  (rwx): ORIGIN = 0x20000000, LENGTH = 22K
+    SRAM (rwx): ORIGIN = 0x10000000, LENGTH = 10K
+}
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))  KEEP(*(.fini))
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o).dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+        *(.rodata*)
+        KEEP(*(.eh_frame*))
+    } > ROM
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+    __etext = .;
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        . = ALIGN(4);
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+        . = ALIGN(4);
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+        . = ALIGN(4);
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+        . = ALIGN(4);
+        __data_end__ = .;
+    } > RAM
+    .bss (NOLOAD) :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    .heap (NOLOAD) :
+    {
+        __end__ = .;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+    .stack_dummy (NOLOAD) :
+    {
+        *(.stack)
+    } > RAM
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+    PROVIDE(_estack = __stack);
+    PROVIDE(_sidata = __etext);
+    PROVIDE(_sdata = __data_start__);
+    PROVIDE(_edata = __data_end__);
+    PROVIDE(_sbss = __bss_start__);
+    PROVIDE(_ebss = __bss_end__);
+}

inc/usb.h

@@ -46,7 +46,8 @@
 
 #elif defined(STM32L432xx) || defined(STM32L433xx) || \
       defined(STM32L442xx) || defined(STM32L443xx) || \
-      defined(STM32L452xx) || defined(STM32L462xx)
+      defined(STM32L452xx) || defined(STM32L462xx) || \
+      defined(STM32G4)
 
     #define USBD_STM32L433
 

readme.md

@@ -26,7 +26,7 @@
         <td>usbd_stm32l052_devfs_asm.S</td>
     </tr>
     <tr>
-        <td rowspan="2">STM32L4x2 STM32L4x3</td>
+        <td rowspan="2">STM32L4x2 STM32L4x3 STM32G4 series</td>
         <td nowrap rowspan="2">Doublebuffered<sup>[2]</sup><br />8<sup>[1]</sup> endpoints<br /> BC1.2</td>
         <td>usbd_devfs</td>
         <td>usbd_stm32l433_devfs.c</td>
@@ -87,7 +87,7 @@
 
 2. At this moment BULK IN endpoint can use both buffers, but it is not **real** doublebuffered.
 
-3. Tested with STM32L052K8, STM32L100RC, STM32L476RG, STM32F072C8, STM32F103C8, STM32F103CB, STM32F303CC, STM32F303RE, STM32F429ZI, STM32F105RBT6, STM32F107VCT6, STM32L433CCT6, STM32F070CBT6
+3. Tested with STM32L052K8, STM32L100RC, STM32L476RG, STM32F072C8, STM32F103C8, STM32F103CB, STM32F303CC, STM32F303RE, STM32F429ZI, STM32F105RBT6, STM32F107VCT6, STM32L433CCT6, STM32F070CBT6, STM32G431RB
 
 ### Implemented definitions for classes ###
 1. USB HID based on [Device Class Definition for Human Interface Devices (HID) Version 1.11](https://www.usb.org/sites/default/files/documents/hid1_11.pdf)

src/memmap.inc

@@ -1,6 +1,6 @@
 /* This file is the part of the Lightweight USB device Stack for STM32 microcontrollers
  *
- * Copyright ©2016 Dmitry Filimonchuk <dmitrystu[at]gmail[dot]com>
+ * Copyright ©2016 Dmitry Filimonchuk <dmitrystu[at]gmail[dot]com>
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -19,7 +19,7 @@
     defined(STM32L082xx) || defined(STM32L083xx) || \
     defined(STM32F042x6) || defined(STM32F048xx) || \
     defined(STM32F070x6) || defined(STM32F070xB) || \
-    defined(STM32F072xB) || defined(STM32F078xx) \
+    defined(STM32F072xB) || defined(STM32F078xx)
 
     #define USB_EPBASE      0x40005C00
     #define USB_REGBASE     0x40005C40
@@ -47,6 +47,7 @@
 #elif defined(STM32L432xx) || defined(STM32L433xx) || \
       defined(STM32L442xx) || defined(STM32L443xx) || \
       defined(STM32L452xx) || defined(STM32L462xx)
+
     #define USB_EPBASE      0x40006800
     #define USB_REGBASE     0x40006840
     #define USB_CNTR        0x00
@@ -62,6 +63,23 @@
     #define UID_BASE        0x1FFF7590
     #define RCC_USBEN       26
 
+#elif defined(STM32G4)
+
+    #define USB_EPBASE      0x40005C00
+    #define USB_REGBASE     0x40005C40
+    #define USB_CNTR        0x00
+    #define USB_ISTR        0x04
+    #define USB_FNR         0x08
+    #define USB_DADDR       0x0C
+    #define USB_BTABLE      0x10
+    #define USB_BCDR        0x18
+    #define USB_PMABASE     0x40006000
+    #define RCC_BASE        0x40021000
+    #define RCC_APB1RSTR    0x38
+    #define RCC_APB1ENR     0x58
+    #define UID_BASE        0x1FFF7590
+    #define RCC_USBEN       23
+
 #elif defined(STM32L1)
 /* common definitions for STM31L100xx STM32L151xx STM32L152xx STM32L162xx */
     #define USB_EPBASE      0x40005C00

src/usbd_stm32l433_devfs.c

@@ -25,6 +25,11 @@
     #define USB_PMASIZE 0x400
 #endif
 
+#if !defined(RCC_APB1ENR1_USBFSEN)
+    #define RCC_APB1ENR1_USBFSEN RCC_APB1ENR1_USBEN
+    #define RCC_APB1RSTR1_USBFSRST RCC_APB1RSTR1_USBRST
+#endif
+
 #define USB_EP_SWBUF_TX     USB_EP_DTOG_RX
 #define USB_EP_SWBUF_RX     USB_EP_DTOG_TX