fix F373

Makefile

@@ -201,4 +201,10 @@ stm32f446xc:  clean
 	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s' \
 						LDSCRIPT='demo/stm32f446xc.ld' \
 						DEFINES='STM32F4 STM32F446xx USBD_SOF_DISABLED' \
+						CFLAGS='-mcpu=cortex-m4'
+
+stm32f373xc: clean
+	@$(MAKE) demo STARTUP='$(CMSISDEV)/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f373xc.s' \
+						LDSCRIPT='demo/stm32f373xc.ld' \
+						DEFINES='STM32F3 STM32F373xC USBD_SOF_DISABLED USBD_ASM_DRIVER' \
 						CFLAGS='-mcpu=cortex-m4'

demo/cdc_startup.c

@@ -84,7 +84,7 @@ static void cdc_init_rcc (void) {
     _BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_1);
     /* use PLL 48MHz clock from 8Mhz HSI */
     _BMD(RCC->CFGR,
-         RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC | RCC_CFGR_USBPRE ,
+         RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC | RCC_CFGR_USBPRE,
          RCC_CFGR_PLLMUL12 | RCC_CFGR_USBPRE);
     _BST(RCC->CR, RCC_CR_PLLON);
     _WBS(RCC->CR, RCC_CR_PLLRDY);
@@ -92,6 +92,27 @@ static void cdc_init_rcc (void) {
     _BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
     _WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL);
 
+#elif defined(STM32F373xC)
+    /* set flash latency 1WS */
+    _BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_1);
+    _BMD(RCC->CFGR,
+         RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC | RCC_CFGR_USBPRE | RCC_CFGR_PPRE1,
+         RCC_CFGR_PLLMUL12  | RCC_CFGR_USBPRE | RCC_CFGR_PPRE1_DIV2);
+    _BST(RCC->CR, RCC_CR_PLLON);
+    _WBS(RCC->CR, RCC_CR_PLLRDY);
+    /* switch to PLL */
+    _BMD(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
+    _WVL(RCC->CFGR, RCC_CFGR_SWS, RCC_CFGR_SWS_PLL);
+
+    /* Enabling USB PA11 PA12 AF 0x0E.
+     * This is still undocumented in the 7th!! revision of the datasheet.
+     * Thank you, mo***rs from ST for extra 5 hrs of debugging.
+     */
+    _BST(RCC->AHBENR, RCC_AHBENR_GPIOAEN);
+    _BST(GPIOA->AFR[1], (0x0E << 12) | (0x0E << 16));
+    _BMD(GPIOA->MODER, (0x03 << 22) | (0x03 << 24), (0x02 << 22) | (0x02 << 24)); // MCO
+
+
 #elif defined(STM32F429xx)
     /* set flash latency 2WS */
     _BMD(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_2WS);

src/memmap.inc

@@ -46,7 +46,7 @@
     #endif
 
     #if defined(STM32F042x6) || defined(STM32F048xx) || \
-        defined(STM32F070x6) 
+        defined(STM32F070x6)
 
         #define SYSCFG_BASE     0x40010000
         #define SYSCFG_USBREMAP 4
@@ -148,7 +148,7 @@
 
 
 #elif defined(STM32F303x8) || defined(STM32F303xC) || \
-      defined(STM32F303xE)
+      defined(STM32F303xE) || defined(STM32F373xC)
 
     #define USB_EPBASE      0x40005C00
     #define USB_REGBASE     0x40005C40