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+/* This file is the part of the Lightweight USB device Stack for STM32 microcontrollers
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+ *
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+ * Copyright ©2016 Dmitry Filimonchuk <dmitrystu[at]gmail[dot]com>
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+ *
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+ * Licensed under the Apache License, Version 2.0 (the "License");
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+ * you may not use this file except in compliance with the License.
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+ * You may obtain a copy of the License at
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+ * http://www.apache.org/licenses/LICENSE-2.0
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+ * Unless required by applicable law or agreed to in writing, software
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+ * distributed under the License is distributed on an "AS IS" BASIS,
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+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+ * See the License for the specific language governing permissions and
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+ * limitations under the License.
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+ */
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+
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+#if !defined (__ASSEMBLER__)
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+ #define __ASSEMBLER__
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+#endif
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+
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+#include "usb.h"
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+#if defined(USE_STMV3_DRIVER)
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+#include "memmap.inc"
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+
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+#define EP_SETUP 0x0800
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+#define EP_TYPE 0x0600
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+#define EP_KIND 0x0100
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+#define EP_ADDR 0x000F
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+
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+#define EP_RX_CTR 0x8000
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+#define EP_RX_DTOG 0x4000
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+#define EP_RX_STAT 0x3000
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+#define EP_RX_SWBUF 0x0040
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+
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+#define EP_RX_DIS 0x0000
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+#define EP_RX_STAL 0x1000
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+#define EP_RX_NAK 0x2000
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+#define EP_RX_VAL 0x3000
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+
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+#define EP_TX_CTR 0x0080
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+#define EP_TX_DTOG 0x0040
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+#define EP_TX_STAT 0x0030
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+#define EP_TX_SWBUF 0x4000
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+
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+#define EP_TX_DIS 0x0000
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+#define EP_TX_STAL 0x0010
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+#define EP_TX_NAK 0x0020
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+#define EP_TX_VAL 0x0030
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+
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+#define RXADDR0 0x00
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+#define RXCOUNT0 0x04
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+#define RXADDR1 0x08
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+#define RXCOUNT1 0x0C
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+
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+#define TXADDR0 0x00
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+#define TXCOUNT0 0x04
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+#define TXADDR1 0x08
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+#define TXCOUNT1 0x0C
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+
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+#define TXADDR 0x00
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+#define TXCOUNT 0x04
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+#define RXADDR 0x08
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+#define RXCOUNT 0x0C
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+
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+
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+
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+#define EP_NOTOG (EP_RX_CTR | EP_TX_CTR | EP_SETUP | EP_TYPE | EP_KIND | EP_ADDR)
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+
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+#define TGL_SET(mask, bits) ((EP_NOTOG | (mask))<<16 | (bits))
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+
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+#define TX_STALL TGL_SET(EP_TX_STAT, EP_TX_STAL)
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+#define RX_STALL TGL_SET(EP_RX_STAT, EP_RX_STAL)
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+#define TX_USTALL TGL_SET(EP_TX_STAT | EP_TX_DTOG, EP_TX_NAK)
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+#define RX_USTALL TGL_SET(EP_RX_STAT | EP_RX_DTOG, EP_RX_VAL)
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+#define DTX_USTALL TGL_SET(EP_TX_STAT | EP_TX_DTOG | EP_TX_SWBUF, EP_TX_VAL)
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+#define DRX_USTALL TGL_SET(EP_RX_STAT | EP_RX_DTOG | EP_RX_SWBUF, EP_RX_VAL | EP_RX_SWBUF)
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+
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+
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+ .syntax unified
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+ .cpu cortex-m3
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+ .text
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+ .thumb
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+
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+
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+ .globl usb_stmv3a
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+ .align 2
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+usb_stmv3a:
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+ .long 0
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+ .long _enable
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+ .long _reset
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+ .long _connect
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+ .long _setaddr
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+ .long _ep_config
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+ .long _ep_deconfig
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+ .long _ep_read
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+ .long _ep_write
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+ .long _ep_setstall
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+ .long _ep_isstalled
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+ .long _evt_poll
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+ .long _get_frame
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+ .long _get_serial_desc
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+ .size usb_stmv3a, . - usb_stmv3a
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+
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+
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+ .thumb_func
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+ .type _get_serial_desc, %function
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+
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+/* uint16_t get_serial_desc (void *buffer)
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+ * R0 <- buffer for the string descriptor
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+ * descrpitor size -> R0
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+ */
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+_get_serial_desc:
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+ push {r4, r5, lr}
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+ movs r1, #18 //descriptor size 18 bytes
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+ strb r1, [r0]
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+ movs r1, #0x03 //DTYPE_STRING
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+ strb r1, [r0, #0x01]
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+ ldr r5, .L_uid_base //UID3 this is the serial number
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+ ldr r4, .L_fnv1a_offset //FNV1A offset
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+ ldr r2, [r5, 0x00] //UID0
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+ bl .L_fnv1a
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+ ldr r2, [r5, 0x04] //UID1
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+ bl .L_fnv1a
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+ ldr r2, [r5, 0x08] //UID2
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+ bl .L_fnv1a
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+ movs r3, #28
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+.L_gsn_loop:
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+ lsrs r1, r4, r3
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+ and r1, #0x0F
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+ cmp r1, #0x09
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+ ite gt
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+ addgt r1, #55
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+ addle r1, #48
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+.L_gsn_store:
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+ adds r0, #0x02
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+ strb r1, [r0]
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+ lsrs r1, #0x08
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+ strb r1, [r0, #0x01]
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+ subs r3, #0x04
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+ bpl .L_gsn_loop
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+ movs r0, #18
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+ pop {r4, r5, pc}
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+
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+.L_fnv1a:
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+ movs r3, #0x04
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+.L_fnv1a_loop:
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+ uxtb r1, r2
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+ eors r4, r1
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+ ldr r1, .L_fnv1a_prime //FNV1A prime
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+ muls r4, r1
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+ lsrs r2, #0x08
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+ subs r3, #0x01
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+ bne .L_fnv1a_loop
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+ bx lr
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+
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+ .align 2
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+.L_uid_base: .long UID_BASE
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+.L_fnv1a_offset: .long 2166136261
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+.L_fnv1a_prime: .long 16777619
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+
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+ .size _get_serial_desc, . - _get_serial_desc
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+
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+ .thumb_func
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+ .type _connect, %function
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+_connect:
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+#if defined(USBD_DP_PORT) && defined(USBD_DP_PIN) && defined(STM32F1)
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+ #if (USBD_DP_PIN < 8)
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+ #define GPIO_CRx GPIO_CRL
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+ #define DP_PIN (4 * USBD_DP_PIN)
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+ #else
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+ #define GPIO_CRx GPIO_CRH
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+ #define DP_PIN (4 * (USBD_DP_PIN - 8))
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+ #endif
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+ ldr r3, =#USBD_DP_PORT
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+ ldr r2, [r3, #GPIO_CRx]
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+ movs r1, #0x0F
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+ bics r2, r2, r1, LSL #DP_PIN
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+ movs r1, #0x04
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+ cbz r0, .L_store
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+ movs r1, #0x01
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+ lsls r1, #USBD_DP_PIN
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+ str r1, [r3, #GPIO_BSRR]
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+ movs r1, #0x02
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+.L_store:
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+ orrs r2, r2, r1, LSL #DP_PIN
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+ str r2, [r3, #GPIO_CRx]
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+#elif defined(USBD_DP_PORT) && defined(USBD_DP_PIN) && defined(STM32F3)
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+ ldr r3, =#USBD_DP_PORT
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+ ldr r2, [r3, #GPIO_MODER]
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+ movs r1, #0x03
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+ bics r2, r2, r1, LSL #(2 * USBD_DP_PIN)
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+ movs r1, #0x01
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+ cbz r0, .L_store
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+ orrs r2, r2, r1, LSL #(2 * USBD_DP_PIN)
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+ lsls r1, #USBD_DP_PIN
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+ str r1, [r3, #GPIO_BSRR]
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+.L_store:
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+ str r2, [r3, #GPIO_MODER]
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+#endif
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+ movs r0, #usbd_lane_unk
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+ bx lr
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+ .size _connect, . - _connect
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+
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+
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+ .thumb_func
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+ .type _setaddr, %function
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+_setaddr:
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+ ldr r1, =#USB_REGBASE
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+ adds r0, #0x80
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+ strh r0, [r1, #USB_DADDR] //USB->DADDR
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+ bx lr
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+ .size _setaddr, . - _setaddr
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+
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+ .thumb_func
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+ .type _reset, %function
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+_reset:
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+ ldr r2, =#USB_REGBASE
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+ movs r0, #0x01 //FRES
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+ ldrh r1, [r2, #USB_CNTR]
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+ orrs r1, r0
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+ strh r1, [r2, #USB_CNTR] // set FRES
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+ bics r1, r0
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+ strh r1, [r2, #USB_CNTR] // clr FRES
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+ bx lr
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+ .size _reset, . - _reset
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+
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+ .thumb_func
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+ .type _get_frame, %function
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+_get_frame:
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+ ldr r0, =#USB_REGBASE
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+ ldrh r0, [r0, #USB_FNR] //FNR
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+ lsls r0, #21
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+ lsrs r0, #21
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+ bx lr
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+ .size _get_frame, . - _get_frame
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+
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+ .thumb_func
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+ .type _enable, %function
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+_enable:
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+ ldr r2, =#RCC_BASE //RCC
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+ movs r3, #0x01
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+ lsls r3, #23 //USBEN or USBRST
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+ cbz r0, .L_disable
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+.L_enable:
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+/* enabling and resetting USB peripheral */
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+ ldr r1, =#USB_REGBASE
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+ ldr r0, [r2, #RCC_APB1ENR]
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+ orrs r0, r3
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+ str r0, [r2, #RCC_APB1ENR] //RCC->APB1ENR |= USBEN
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+ ldr r0, [r2, #RCC_APB1RSTR]
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+ orrs r0, r3
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+ str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR |= USBRST
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+ bics r0, r3
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+ str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR &= ~USBRST
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+/* setting up USB CNTR */
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+#if !defined(USBD_SOF_DISABLED)
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+ movs r0, #0xBE // CTRM | ERRM | WKUPM | SUSPM | RESETM | SOFM
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+#else
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+ movs r0, #0xBC // CTRM | ERRM | WKUPM | SUSPM | RESETM
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+#endif
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+ lsls r0, #0x08
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+ strh r0, [r1, #USB_CNTR] //set USB->CNTR
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+ bx lr
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+.L_disable:
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+ ldr r0, [r2, #RCC_APB1ENR]
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+ tst r0, r3
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+ beq .L_enable_end // usb is already disabled
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+/* disabling USB peripheral */
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+ bics r0, r3
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+ str r0, [r2, #RCC_APB1ENR]
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+ movs r0, #0
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+ b _connect // jump to disconnect subroutine
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+.L_enable_end:
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+ bx lr
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+ .size _enable, . - _enable
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+
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+ .thumb_func
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+ .type _ep_setstall, %function
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+
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+/*void ep_settall(uint8_t ep, bool stall)
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+ * in R0 <- endpoint number
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+ * in R1 <- 0 if unstall, !0 if stall
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+ */
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+_ep_setstall:
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+ push {r4, lr}
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+ lsls r2, r0, #28
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+ lsrs r2, #26
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+ ldr r3, =#USB_EPBASE
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+ adds r3, r2 // epr -> r3
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+ movs r2, 0x30 // TX_STAT_MASK -> r2
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+ ldrh r4, [r3]
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+ lsls r4, #21
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+ lsrs r4, #29 // EP_TYPE | EP_KIND -> R4 LSB
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+ cmp r4, #0x04 // ISO ?
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+ beq .L_eps_exit
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+ cmp r0, #0x80
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+ blo .L_eps_rx
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+.L_eps_tx:
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+ ldr r0, =#TX_STALL //stall TX
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+ cmp r1, #0x00
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+ bne .L_eps_reg_set
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+.L_eps_tx_unstall:
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+ ldr r0, =#DTX_USTALL //unstall dblbulk or iso TX (VALID and clr DTOG_TX & SWBUF_TX)
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+ cmp r4, #0x01 // if doublebuffered bulk endpoint
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+ beq .L_eps_reg_set
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+ ldr r0, =#TX_USTALL // unstall other TX (NAKED + clr DTOG_TX)
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+ b .L_eps_reg_set
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+.L_eps_rx:
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+ lsls r2, #8 // RX_STAT_MASK -> R2
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+ ldr r0,=#RX_STALL //stall RX
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+ cmp r1, #0x00
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+ bne .L_eps_reg_set
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+.L_eps_rx_unstall:
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+ ldr r0, =#DRX_USTALL //unstall dblbulk or iso (VALID. clr DTOG_RX set SWBUF_RX)
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+ cmp r4, #0x01 // if dblbulk
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+ beq .L_eps_reg_set
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+ ldr r0, =#RX_USTALL // unstall other RX (VALID + clr
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+/* R0 - mask and toggle bits
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+ * R2 - mask for STAT bits
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+ * R3 - endpoint register pointer
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+ */
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+.L_eps_reg_set:
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+ ldrh r1, [r3] // *epr -> r1
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+ ands r2, r1 // check if endpoint disabled
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+ beq .L_eps_exit // do nothing
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+ eors r1, r0
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+ lsrs r0, #16
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+ ands r1, r0
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+ strh r1, [r3]
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+.L_eps_exit:
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+ pop {r4, pc}
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+ .size _ep_setstall, . - _ep_setstall
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+
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+
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+ .thumb_func
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+ .type _ep_isstalled, %function
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+/* bool ep_isstalled(uint8t ep) */
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+_ep_isstalled:
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+ ldr r1, =#USB_EPBASE
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+ lsls r2, r0, #28
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+ lsrs r2, #26
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+ ldr r1, [r1, r2]
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+ lsls r1, #17
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+ cmp r0, #0x80
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+ bhs .L_eis_check
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+ lsls r1, #8
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+.L_eis_check:
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+ lsrs r1, r1, #28
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+ subs r1, #0x01
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+ subs r0, r1, #0x01
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+ sbcs r1, r1
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+ rsbs r0, r1, #0
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+ bx lr
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+ .size _ep_isstalled, . - _ep_isstalled
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+
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+
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+ .thumb_func
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+ .type _ep_read, %function
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+/* int32_t _ep_read(uint8_t ep, void *buf, uint16_t blen)
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+ * in R0 <- endpoint
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+ * in R1 <- *buffer
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+ * in R2 <- length of the buffer
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+ * out length of the recieved data -> R0 or 0 on error
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+ */
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+_ep_read:
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+ push {r4, r5, lr}
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+ ldr r3, =#USB_EPBASE
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+ ldr r4, =#USB_PMABASE
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+ lsls r0, #28
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+ add r3, r3, r0, LSR #26 //*EPR -> R3
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+ add r4, r4, r0, LSR #24 //*EPT -> R4
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+ ldrh r5, [r3] // reading epr
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+/* validating endpoint */
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+ movs r0, #0x37
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+ ands r0, r0, r5, LSR #8
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+ cmp r0, #0x34 // (OK) RX_VALID + ISO
|
|
|
+ beq .L_epr_iso
|
|
|
+ cmp r0, #0x31 // (OK) RX_VALID + DBLBULK
|
|
|
+ beq .L_epr_dbl
|
|
|
+ cmp r0, #0x20 // (OK) RX_NAKED + BULK
|
|
|
+ beq .L_epr_sngl
|
|
|
+ cmp r0, #0x22 // (OK) RX_NAKED + CTRL
|
|
|
+ beq .L_epr_sngl
|
|
|
+ cmp r0, #0x26 // (OK) RX_NAKED + INTR
|
|
|
+ beq .L_epr_sngl
|
|
|
+ movs r0, #0xFF // endpoint contains no valid data
|
|
|
+ sxtb r0, r0
|
|
|
+ b .L_epr_exit
|
|
|
+/* processing */
|
|
|
+.L_epr_dbl:
|
|
|
+// lsrs r0, r5, #8
|
|
|
+// eors r0, r5
|
|
|
+ eors r0, r5, r5, LSR #8
|
|
|
+ lsrs r0, #7 // SW_RX ^ DTOG_RX -> CF
|
|
|
+ bcs .L_epr_notog // jmp if SW_RX != DTOG_RX (VALID)
|
|
|
+ ldr r0, =#EP_NOTOG
|
|
|
+ ands r5, r0
|
|
|
+ adds r5, #EP_RX_SWBUF
|
|
|
+ strh r5, [r3] // toggling SW_RX
|
|
|
+.L_epr_notog:
|
|
|
+ ldrh r5, [r3]
|
|
|
+ lsls r5, #8 // shift SW_RX to DTOG_RX
|
|
|
+.L_epr_iso:
|
|
|
+ lsrs r5, #15 // DTOG_RX -> CF
|
|
|
+ bcs .L_epr_sngl
|
|
|
+ subs r4, #0x08 // set RXADDR0
|
|
|
+.L_epr_sngl:
|
|
|
+ ldrh r0, [r4, #RXCOUNT]
|
|
|
+ lsrs r5, r0, #0x0A
|
|
|
+ lsls r5, #0x0A // r5 = r5 & ~0x03FF
|
|
|
+ strh r5, [r4, #RXCOUNT]
|
|
|
+ lsls r0, #22
|
|
|
+ lsrs r0, #22 // r0 &= 0x3FF (RX count)
|
|
|
+ ldrh r5, [r4, #RXADDR]
|
|
|
+ ldr r4, =#USB_PMABASE
|
|
|
+ lsls r5, #0x01
|
|
|
+ adds r5, r4 // R5 now has a physical address
|
|
|
+ cmp r2, r0
|
|
|
+ blo .L_epr_read
|
|
|
+ mov r2, r0 // if buffer is larger
|
|
|
+.L_epr_read:
|
|
|
+ cmp r2, #1
|
|
|
+ blo .L_epr_read_end
|
|
|
+ ldrh r4, [r5]
|
|
|
+ strb r4, [r1]
|
|
|
+ beq .L_epr_read_end
|
|
|
+ lsrs r4, #8
|
|
|
+ strb r4, [r1, #1]
|
|
|
+ adds r1, #2
|
|
|
+ adds r5, #4
|
|
|
+ subs r2, #2
|
|
|
+ bhi .L_epr_read
|
|
|
+.L_epr_read_end:
|
|
|
+ ldrh r5, [r3] // reload EPR
|
|
|
+ lsls r1, r5, #21
|
|
|
+ lsrs r1, #29
|
|
|
+ cmp r1, #0x04
|
|
|
+ beq .L_epr_exit // ep is iso. no needs to set it to valid
|
|
|
+ cmp r1, #0x01
|
|
|
+ beq .L_epr_exit // ep is dblbulk. no needs to set it to valid
|
|
|
+ ldr r2, =#TGL_SET(EP_RX_STAT , EP_RX_VAL)
|
|
|
+ eors r5, r2
|
|
|
+ and r5, r5, r2, LSR #16
|
|
|
+ strh r5, [r3] // set ep to VALID state
|
|
|
+.L_epr_exit:
|
|
|
+ pop {r4, r5, pc}
|
|
|
+ .size _ep_read, . - _ep_read
|
|
|
+
|
|
|
+
|
|
|
+ .thumb_func
|
|
|
+ .type _ep_write, %function
|
|
|
+/* int32_t ep_write(uint8_t ep, void *buf, uint16_t blen)
|
|
|
+ * R0 -> endpoint
|
|
|
+ * R1 -> *buffer
|
|
|
+ * R2 -> data length
|
|
|
+ * result -> R0
|
|
|
+ */
|
|
|
+_ep_write:
|
|
|
+ push {r4, r5, r6, lr}
|
|
|
+ ldr r3, =#USB_EPBASE
|
|
|
+ ldr r4, =#USB_PMABASE
|
|
|
+ lsls r0, #28
|
|
|
+ add r3, r3, r0, LSR #26 //*EPR -> R3
|
|
|
+ add r4, r4, r0, LSR #24 //*EPT -> R4
|
|
|
+ ldrh r5, [r3] // reading epr
|
|
|
+ movs r0, #0x73
|
|
|
+ and r0, r0, r5, LSR #4
|
|
|
+ cmp r0, #0x43 // (OK) TX_VALID + ISO
|
|
|
+ beq .L_epw_iso
|
|
|
+ cmp r0, #0x12 // (OK) TX_NAK + DBLBULK
|
|
|
+ beq .L_epw_dbl
|
|
|
+ cmp r0, #0x02 // (OK) TX_NAK + BULK
|
|
|
+ beq .L_epw_sngl
|
|
|
+ cmp r0, #0x22 // (OK) TX_NAK + CONTROL
|
|
|
+ beq .L_epw_sngl
|
|
|
+ cmp r0, #0x62 // (OK) TX_NAK + INTERRUPT
|
|
|
+ beq .L_epw_sngl
|
|
|
+ movs r0, #0xFF // -1 error
|
|
|
+ sxtb r0, r0
|
|
|
+ b .L_epw_exit
|
|
|
+.L_epw_dbl:
|
|
|
+ mvns r5, r5
|
|
|
+ lsrs r5, #8 // ~SWBUF_TX -> DTOG_TX
|
|
|
+.L_epw_iso:
|
|
|
+ lsrs r5, #7 // DTOG_TX -> CF
|
|
|
+ bcs .L_epw_sngl
|
|
|
+ adds r4, #8 // TXADDR1 -> R4
|
|
|
+.L_epw_sngl:
|
|
|
+ strh r2, [r4, #TXCOUNT]
|
|
|
+ mov r0, r2 // save count for return
|
|
|
+ ldrh r5, [r4, #TXADDR]
|
|
|
+ ldr r4, =#USB_PMABASE
|
|
|
+ lsls r5, #1
|
|
|
+ adds r5, r4 // PMA BUFFER -> R5
|
|
|
+.L_epw_write:
|
|
|
+ cmp r2, #1
|
|
|
+ blo .L_epw_write_end
|
|
|
+ ldrb r4, [r1]
|
|
|
+ beq .L_epw_store
|
|
|
+ ldrb r6, [r1, #1]
|
|
|
+ lsls r6, #8
|
|
|
+ orrs r4, r6
|
|
|
+.L_epw_store:
|
|
|
+ strh r4, [r5]
|
|
|
+ adds r5, #4
|
|
|
+ adds r1, #2
|
|
|
+ subs r2, #2
|
|
|
+ bhi .L_epw_write
|
|
|
+.L_epw_write_end:
|
|
|
+ ldrh r5, [r3] // reload EPR
|
|
|
+ lsls r1, r5, #21
|
|
|
+ lsrs r1, #29
|
|
|
+ cmp r1, #0x04
|
|
|
+ beq .L_epw_exit // isochronous ep. do nothing
|
|
|
+ ldr r2, =#TGL_SET(EP_TX_STAT, EP_TX_VAL)
|
|
|
+ cmp r1, #0x01
|
|
|
+ bne .L_epw_setstate // NOT a doublebuffered bulk
|
|
|
+ ldr r2, =#TGL_SET(EP_TX_SWBUF, EP_TX_SWBUF)
|
|
|
+ bics r5, r2 // clear TX_SWBUF
|
|
|
+.L_epw_setstate:
|
|
|
+ eors r5, r2
|
|
|
+// lsrs r2, #16
|
|
|
+// ands r5, r2
|
|
|
+ and r5, r5, r2, LSR #16
|
|
|
+ strh r5, [r3]
|
|
|
+.L_epw_exit:
|
|
|
+ pop {r4, r5, r6, pc}
|
|
|
+ .size _ep_write, .- _ep_write
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+/* internal function */
|
|
|
+/* requester size passed in R2 */
|
|
|
+/* result returns in R0 CF=1 if OK*/
|
|
|
+
|
|
|
+_get_next_pma:
|
|
|
+ push {r1, r3, r4, lr}
|
|
|
+ movs r1, #16
|
|
|
+ movs r3, #1
|
|
|
+ lsls r3, #9 //R3 MAX_PMA_SIZE 512b
|
|
|
+ ldr r0, =#USB_PMABASE
|
|
|
+.L_gnp_chkaddr:
|
|
|
+ ldrh r4, [r0, #0] //txaddr
|
|
|
+ tst r4, r4
|
|
|
+ beq .L_gnp_nxtaddr
|
|
|
+ cmp r3, r4
|
|
|
+ blo .L_gnp_nxtaddr
|
|
|
+ mov r3, r4
|
|
|
+.L_gnp_nxtaddr:
|
|
|
+ adds r0, #8
|
|
|
+ subs r1, #1
|
|
|
+ bne .L_gnp_chkaddr
|
|
|
+ subs r0, r3, r2
|
|
|
+ blo .L_gnp_exit
|
|
|
+ cmp r0, #0x40 //check for the pma table overlap
|
|
|
+.L_gnp_exit:
|
|
|
+ pop {r1, r3, r4, pc}
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+ .size _get_next_pma, . - _get_next_pma
|
|
|
+
|
|
|
+ .thumb_func
|
|
|
+ .type _ep_config, %function
|
|
|
+/* bool ep_config(uint8_t ep, uint8_t eptype, uint16_t epsize)
|
|
|
+ * R0 <- ep
|
|
|
+ * R1 <- eptype
|
|
|
+ * R2 <- epsize
|
|
|
+ * result -> R0
|
|
|
+ */
|
|
|
+_ep_config:
|
|
|
+ push {r4, r5, lr}
|
|
|
+ movs r3, 0x01
|
|
|
+ ands r3, r2
|
|
|
+ adds r2, r3 //R2 -> halfword aligned epsize
|
|
|
+ movs r3, #0x00 //BULK
|
|
|
+ cmp r1, #0x02 // is eptype bulk ?
|
|
|
+ beq .L_epc_settype
|
|
|
+ movs r3, #0x01 //DBLBULK
|
|
|
+ cmp r1, #0x06
|
|
|
+ beq .L_epc_settype
|
|
|
+ movs r3, #0x02 //CONTROL
|
|
|
+ cmp r1, #0x00
|
|
|
+ beq .L_epc_settype
|
|
|
+ movs r3, #0x04 //ISO
|
|
|
+ cmp r1, #0x01
|
|
|
+ beq .L_epc_settype
|
|
|
+ movs r3, #0x06 //INTERRUPT
|
|
|
+.L_epc_settype:
|
|
|
+ lsls r3, #8
|
|
|
+ lsls r4, r0, #28
|
|
|
+ lsrs r4, #28
|
|
|
+ orrs r3, r4
|
|
|
+ lsls r4, #2
|
|
|
+ ldr r5, =#USB_EPBASE
|
|
|
+ strh r3, [r5, r4] //setup EPTYPE EPKIND EPADDR
|
|
|
+ cmp r1, #0x00 // is a control ep ?
|
|
|
+ beq .L_epc_setuptx
|
|
|
+ cmp r0, #0x80
|
|
|
+ blo .L_epc_setuprx
|
|
|
+.L_epc_setuptx:
|
|
|
+ ldr r5, =#USB_PMABASE
|
|
|
+ lsls r4, #2
|
|
|
+ adds r5, r4
|
|
|
+ bl _get_next_pma
|
|
|
+ bcc .L_epc_fail
|
|
|
+ strh r0, [r5, #TXADDR] //store txaddr or txaddr0
|
|
|
+ movs r0, #0x00
|
|
|
+ strh r0, [r5, #TXCOUNT] //store txcnt
|
|
|
+ cmp r1, #0x06 // is DBLBULK
|
|
|
+ beq .L_epc_txdbl
|
|
|
+ ldr r3, =#TX_USTALL //set state NAKED , clr DTOG_TX
|
|
|
+ cmp r1, #0x01 // is ISO
|
|
|
+ bne .L_epc_txsetstate //
|
|
|
+.L_epc_txdbl:
|
|
|
+ ldr r3, =#DTX_USTALL //set state VALID clr DTOG_TX & SWBUF_TX
|
|
|
+ bl _get_next_pma
|
|
|
+ bcc .L_epc_fail
|
|
|
+ strh r0, [r5, #TXADDR1] //store txaddr1
|
|
|
+ movs r0, #0x00
|
|
|
+ strh r0, [r5, #TXCOUNT1] //store txcnt
|
|
|
+.L_epc_txsetstate:
|
|
|
+ ldr r5, =#USB_EPBASE
|
|
|
+ lsrs r4, #2
|
|
|
+ ldrh r0, [r5, r4]
|
|
|
+ eors r0, r3
|
|
|
+ lsrs r3, #16
|
|
|
+ ands r0, r3
|
|
|
+ strh r0, [r5, r4]
|
|
|
+ cmp r1, #0x00 //is a control ep ?
|
|
|
+ bne .L_epc_exit
|
|
|
+.L_epc_setuprx:
|
|
|
+ mov r3, r2
|
|
|
+ cmp r2, #62
|
|
|
+ bls .L_epc_rxbb
|
|
|
+ movs r3, #0x1F
|
|
|
+ ands r3, r2
|
|
|
+ bne .L_epc_rxaa
|
|
|
+ subs r2, #0x20
|
|
|
+.L_epc_rxaa:
|
|
|
+ bics r2, r3
|
|
|
+ lsrs r3, r2, #4
|
|
|
+ adds r3, #0x40
|
|
|
+ adds r2, #0x20
|
|
|
+.L_epc_rxbb:
|
|
|
+ lsls r3, #9
|
|
|
+ ldr r5, =#USB_PMABASE
|
|
|
+ lsls r4, #2
|
|
|
+ adds r5, r4
|
|
|
+/* RX or RX1 */
|
|
|
+ bl _get_next_pma
|
|
|
+ bcc .L_epc_fail
|
|
|
+ strh r0, [r5, #RXADDR]
|
|
|
+ strh r3, [r5, #RXCOUNT]
|
|
|
+ ldr r0, =#RX_USTALL
|
|
|
+/* check if doublebuffered */
|
|
|
+ cmp r1, 0x06 //if dblbulk
|
|
|
+ beq .L_epc_rxdbl
|
|
|
+ cmp r1, 0x01 // iso
|
|
|
+ bne .L_epc_rxsetstate
|
|
|
+.L_epc_rxdbl:
|
|
|
+ bl _get_next_pma
|
|
|
+ bcc .L_epc_fail
|
|
|
+ strh r0, [r5, #RXADDR0] //store rxaddr0
|
|
|
+ strh r3, [r5, #RXCOUNT0] //store rxcnt0
|
|
|
+ ldr r0, =#DRX_USTALL
|
|
|
+.L_epc_rxsetstate:
|
|
|
+ ldr r5, =#USB_EPBASE
|
|
|
+ lsrs r4, #2
|
|
|
+ ldrh r3, [r5, r4]
|
|
|
+ eors r3, r0
|
|
|
+ lsrs r0, #16
|
|
|
+ ands r3, r0
|
|
|
+ strh r3, [r5, r4]
|
|
|
+.L_epc_exit:
|
|
|
+ movs r0, #0x01
|
|
|
+ pop {r4, r5, pc}
|
|
|
+.L_epc_fail:
|
|
|
+ movs r0, #0x00
|
|
|
+ pop {r4, r5, pc}
|
|
|
+
|
|
|
+ .size _ep_config, . - _ep_config
|
|
|
+
|
|
|
+ .thumb_func
|
|
|
+ .type _ep_deconfig, %function
|
|
|
+
|
|
|
+
|
|
|
+/* void ep_deconfig( uint8_t ep)
|
|
|
+ * R0 <- ep
|
|
|
+ */
|
|
|
+_ep_deconfig:
|
|
|
+ lsls r1, r0, #28
|
|
|
+ lsrs r1, #26
|
|
|
+ ldr r2, =#USB_EPBASE
|
|
|
+ ldr r3, =#USB_PMABASE
|
|
|
+ adds r2, r1
|
|
|
+ lsls r1, #1
|
|
|
+ adds r3, r1
|
|
|
+/* clearing endpoint register */
|
|
|
+ ldr r1, =#EP_NOTOG
|
|
|
+ ldrh r0, [r2]
|
|
|
+ bics r0, r1
|
|
|
+ strh r0, [r2]
|
|
|
+/* clearing PMA data */
|
|
|
+ movs r0, #0x00
|
|
|
+ strh r0, [r3, #TXADDR]
|
|
|
+ strh r0, [r3, #TXCOUNT]
|
|
|
+ strh r0, [r3, #RXADDR]
|
|
|
+ strh r0, [r3, #RXCOUNT]
|
|
|
+ bx lr
|
|
|
+
|
|
|
+ .size _ep_deconfig, . - _ep_config
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+#define ISTRSHIFT 8
|
|
|
+#define ISTRBIT(bit) ((1 << bit) >> ISTRSHIFT)
|
|
|
+
|
|
|
+
|
|
|
+ .thumb_func
|
|
|
+ .type _evt_poll, %function
|
|
|
+/*void evt_poll(usbd_device *dev, usbd_evt_callback callback)*/
|
|
|
+_evt_poll:
|
|
|
+ push {r0, r1, r4, r5}
|
|
|
+ ldr r3, =#USB_REGBASE
|
|
|
+ ldrh r0, [r3, #4] //USB->ISTR -> R2
|
|
|
+/* ep_index -> R2 */
|
|
|
+ movs r2, 0x07
|
|
|
+ ands r2, r0
|
|
|
+/* checking USB->ISTR for events */
|
|
|
+#if !defined(USBD_SOF_DISABLED)
|
|
|
+ lsrs r1, r0, #10 //SOFM -> CF
|
|
|
+ bcs .L_ep_sofm
|
|
|
+#endif
|
|
|
+ lsrs r1, r0, #11 //RESETM -> CF
|
|
|
+ bcs .L_ep_resetm
|
|
|
+ lsrs r1, r0, #16 //CTRM -> CF
|
|
|
+ bcs .L_ep_ctrm
|
|
|
+ lsrs r1, r0, #14 //ERRM -> CF
|
|
|
+ bcs .L_ep_errm
|
|
|
+ lsrs r1, r0, #13 //WKUPM -> CF
|
|
|
+ bcs .L_ep_wkupm
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+ lsrs r1, r0, #12 //SUSPM -> CF
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+ bcs .L_ep_suspm
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+ /* exit with no callback */
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+ pop {r0, r1, r4 , r5}
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+ bx lr
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+
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+.L_ep_ctrm:
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+ movs r5, #0x80 // CTR_TX mask to R5
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+ ldr r0,=#USB_EPBASE
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+// lsrs r0, #2
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+// adds r0, r2
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+// lsls r0, #2 // R0 ep register address
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+ add r0, r0, r2, LSL #2 // R0 ep register address
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+ ldrh r4, [r0] // R4 EPR valur
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+ lsrs r3, r4, #8 // CTR_TX -> CF
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+ bcc .L_ep_ctr_rx
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+/* CTR_TX event */
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+ movs r1, #usbd_evt_eptx
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+ orrs r2, r5 // set endpoint tx
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+ b .L_ep_clr_ctr
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+.L_ep_ctr_rx:
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+/* CTR_RX RX or SETUP */
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+ lsls r5, #0x08 // set mask to CRT_RX
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+ movs r1, #usbd_evt_eprx
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+ lsls r3, r4, #21 //SETUP -> CF
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|
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+ bcc .L_ep_clr_ctr
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|
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+ movs r1, #usbd_evt_epsetup
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+.L_ep_clr_ctr:
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+ bics r4, r5 //clear CTR flag
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+ ldr r5, =#EP_NOTOG
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+ ands r4, r5
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+ strh r4, [r0] // store
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+ b .L_ep_callback
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|
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+.L_ep_errm:
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|
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+ movs r1, #usbd_evt_error
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|
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+ movs r4, #ISTRBIT(13)
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|
|
+ b .L_ep_clristr
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|
|
+#if !defined(USBD_SOF_DISABLED)
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|
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+.L_ep_sofm:
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|
|
+ movs r1, #usbd_evt_sof
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|
|
+ movs r4, #ISTRBIT(9)
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|
|
+ b .L_ep_clristr
|
|
|
+#endif
|
|
|
+.L_ep_wkupm:
|
|
|
+ ldrh r1, [r3, #0] //R1 USB->CNTR
|
|
|
+ movs r5, #0x08
|
|
|
+ bics r1, r5 //clr FSUSP
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|
|
+ strh r1, [r3, #0] //USB->CNTR R2
|
|
|
+ movs r1, #usbd_evt_wkup
|
|
|
+ movs r4, #ISTRBIT(12)
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|
|
+ b .L_ep_clristr
|
|
|
+
|
|
|
+.L_ep_suspm:
|
|
|
+ ldrh r1, [r3, #0] //R1 USB->CNTR
|
|
|
+ movs r5, #0x08
|
|
|
+ orrs r1, r5 //set FSUSP
|
|
|
+ strh r1, [r3, #0] //USB->CNTR R2
|
|
|
+ movs r1, #usbd_evt_susp
|
|
|
+ movs r4, #ISTRBIT(11)
|
|
|
+ b .L_ep_clristr
|
|
|
+
|
|
|
+/* do reset routine */
|
|
|
+.L_ep_resetm:
|
|
|
+ movs r1, #7
|
|
|
+ ldr r2, =#USB_EPBASE
|
|
|
+ ldr r0, =#USB_PMABASE
|
|
|
+ ldr r5, =#EP_NOTOG
|
|
|
+.L_ep_reset_loop:
|
|
|
+ ldrh r4, [r2]
|
|
|
+ bics r4, r5
|
|
|
+ strh r4, [r2]
|
|
|
+ movs r4, #0
|
|
|
+ strh r4, [r0, #TXADDR]
|
|
|
+ strh r4, [r0, #TXCOUNT]
|
|
|
+ strh r4, [r0, #RXADDR]
|
|
|
+ strh r4, [r0, #RXCOUNT]
|
|
|
+ adds r2, #0x04
|
|
|
+ adds r0, #0x10
|
|
|
+ subs r1, #1
|
|
|
+ bpl .L_ep_reset_loop
|
|
|
+ movs r2, #0x00
|
|
|
+ strh r2, [r3, #0x10] // 0 -> USB->BTABLE
|
|
|
+ movs r1, #usbd_evt_reset
|
|
|
+ movs r4, #ISTRBIT(10)
|
|
|
+.L_ep_clristr:
|
|
|
+ lsls r4, #ISTRSHIFT
|
|
|
+ ldrh r0, [r3, #4]
|
|
|
+ bics r0, r4
|
|
|
+ strh r0, [r3, #4]
|
|
|
+.L_ep_callback:
|
|
|
+ pop {r0, r3, r4, r5 }
|
|
|
+ bx r3
|
|
|
+
|
|
|
+ .size _evt_poll, . - _evt_poll
|
|
|
+
|
|
|
+ .pool
|
|
|
+
|
|
|
+ .end
|
|
|
+
|
|
|
+#endif
|
Maxthon Chan