usbd_stm32l100_devfs_asm.S 22 KB

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  1. /* This file is the part of the Lightweight USB device Stack for STM32 microcontrollers
  2. *
  3. * Copyright ©2016 Dmitry Filimonchuk <dmitrystu[at]gmail[dot]com>
  4. *
  5. * Licensed under the Apache License, Version 2.0 (the "License");
  6. * you may not use this file except in compliance with the License.
  7. * You may obtain a copy of the License at
  8. * http://www.apache.org/licenses/LICENSE-2.0
  9. * Unless required by applicable law or agreed to in writing, software
  10. * distributed under the License is distributed on an "AS IS" BASIS,
  11. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. * See the License for the specific language governing permissions and
  13. * limitations under the License.
  14. */
  15. #if !defined (__ASSEMBLER__)
  16. #define __ASSEMBLER__
  17. #endif
  18. #include "usb.h"
  19. #if defined(USE_STMV1_DRIVER)
  20. #include "memmap.inc"
  21. #define EP_SETUP 0x0800
  22. #define EP_TYPE 0x0600
  23. #define EP_KIND 0x0100
  24. #define EP_ADDR 0x000F
  25. #define EP_RX_CTR 0x8000
  26. #define EP_RX_DTOG 0x4000
  27. #define EP_RX_STAT 0x3000
  28. #define EP_RX_SWBUF 0x0040
  29. #define EP_RX_DIS 0x0000
  30. #define EP_RX_STAL 0x1000
  31. #define EP_RX_NAK 0x2000
  32. #define EP_RX_VAL 0x3000
  33. #define EP_TX_CTR 0x0080
  34. #define EP_TX_DTOG 0x0040
  35. #define EP_TX_STAT 0x0030
  36. #define EP_TX_SWBUF 0x4000
  37. #define EP_TX_DIS 0x0000
  38. #define EP_TX_STAL 0x0010
  39. #define EP_TX_NAK 0x0020
  40. #define EP_TX_VAL 0x0030
  41. #define RXADDR0 0x00
  42. #define RXCOUNT0 0x04
  43. #define RXADDR1 0x08
  44. #define RXCOUNT1 0x0C
  45. #define TXADDR0 0x00
  46. #define TXCOUNT0 0x04
  47. #define TXADDR1 0x08
  48. #define TXCOUNT1 0x0C
  49. #define TXADDR 0x00
  50. #define TXCOUNT 0x04
  51. #define RXADDR 0x08
  52. #define RXCOUNT 0x0C
  53. #define EP_NOTOG (EP_RX_CTR | EP_TX_CTR | EP_SETUP | EP_TYPE | EP_KIND | EP_ADDR)
  54. #define TGL_SET(mask, bits) ((EP_NOTOG | (mask))<<16 | (bits))
  55. #define TX_STALL TGL_SET(EP_TX_STAT, EP_TX_STAL)
  56. #define RX_STALL TGL_SET(EP_RX_STAT, EP_RX_STAL)
  57. #define TX_USTALL TGL_SET(EP_TX_STAT | EP_TX_DTOG, EP_TX_NAK)
  58. #define RX_USTALL TGL_SET(EP_RX_STAT | EP_RX_DTOG, EP_RX_VAL)
  59. #define DTX_USTALL TGL_SET(EP_TX_STAT | EP_TX_DTOG | EP_TX_SWBUF, EP_TX_VAL)
  60. #define DRX_USTALL TGL_SET(EP_RX_STAT | EP_RX_DTOG | EP_RX_SWBUF, EP_RX_VAL | EP_RX_SWBUF)
  61. .syntax unified
  62. .cpu cortex-m3
  63. .text
  64. .thumb
  65. .globl usb_stmv1a
  66. .align 2
  67. usb_stmv1a:
  68. .long 0
  69. .long _enable
  70. .long _reset
  71. .long _connect
  72. .long _setaddr
  73. .long _ep_config
  74. .long _ep_deconfig
  75. .long _ep_read
  76. .long _ep_write
  77. .long _ep_setstall
  78. .long _ep_isstalled
  79. .long _evt_poll
  80. .long _get_frame
  81. .long _get_serial_desc
  82. .size usb_stmv1a, . - usb_stmv1a
  83. .thumb_func
  84. .type _get_serial_desc, %function
  85. /* uint16_t get_serial_desc (void *buffer)
  86. * R0 <- buffer for the string descriptor
  87. * descrpitor size -> R0
  88. */
  89. _get_serial_desc:
  90. push {r4, r5, lr}
  91. movs r1, #18 //descriptor size 18 bytes
  92. strb r1, [r0]
  93. movs r1, #0x03 //DTYPE_STRING
  94. strb r1, [r0, #0x01]
  95. ldr r5, .L_uid_base //UID3 this is the serial number
  96. ldr r4, .L_fnv1a_offset //FNV1A offset
  97. ldr r2, [r5, 0x00] //UID0
  98. bl .L_fnv1a
  99. ldr r2, [r5, 0x04] //UID1
  100. bl .L_fnv1a
  101. ldr r2, [r5, 0x14] //UID2
  102. bl .L_fnv1a
  103. movs r3, #28
  104. .L_gsn_loop:
  105. lsrs r1, r4, r3
  106. and r1, #0x0F
  107. cmp r1, #0x09
  108. ite gt
  109. addgt r1, #55
  110. addle r1, #48
  111. .L_gsn_store:
  112. adds r0, #0x02
  113. strb r1, [r0]
  114. lsrs r1, #0x08
  115. strb r1, [r0, #0x01]
  116. subs r3, #0x04
  117. bpl .L_gsn_loop
  118. movs r0, #18
  119. pop {r4, r5, pc}
  120. .L_fnv1a:
  121. movs r3, #0x04
  122. .L_fnv1a_loop:
  123. uxtb r1, r2
  124. eors r4, r1
  125. ldr r1, .L_fnv1a_prime //FNV1A prime
  126. muls r4, r1
  127. lsrs r2, #0x08
  128. subs r3, #0x01
  129. bne .L_fnv1a_loop
  130. bx lr
  131. .align 2
  132. .L_uid_base: .long UID_BASE
  133. .L_fnv1a_offset: .long 2166136261
  134. .L_fnv1a_prime: .long 16777619
  135. .size _get_serial_desc, . - _get_serial_desc
  136. .thumb_func
  137. .type _connect, %function
  138. _connect:
  139. ldr r1, =#SYSCFG_BASE
  140. movs r3, #0x01
  141. ldr r2, [r1, #SYSCFG_PMC]
  142. bics r2, r3
  143. cbz r0, .L_conn_store
  144. orrs r2, r3
  145. .L_conn_store:
  146. str r2, [r1, #SYSCFG_PMC]
  147. movs r0, #usbd_lane_unk
  148. bx lr
  149. .size _connect, . - _connect
  150. .thumb_func
  151. .type _setaddr, %function
  152. _setaddr:
  153. ldr r1, =USB_REGBASE
  154. adds r0, #0x80
  155. strh r0, [r1, #USB_DADDR] //USB->DADDR
  156. bx lr
  157. .size _setaddr, . - _setaddr
  158. .thumb_func
  159. .type _reset, %function
  160. _reset:
  161. ldr r2, =#USB_REGBASE
  162. movs r0, #0x01 //FRES
  163. ldrh r1, [r2, #USB_CNTR]
  164. orrs r1, r0
  165. strh r1, [r2, #USB_CNTR] // set FRES
  166. bics r1, r0
  167. strh r1, [r2, #USB_CNTR] // clr FRES
  168. bx lr
  169. .size _reset, . - _reset
  170. .thumb_func
  171. .type _get_frame, %function
  172. _get_frame:
  173. ldr r0, =#USB_REGBASE
  174. ldrh r0, [r0, #USB_FNR] //FNR
  175. lsls r0, #21
  176. lsrs r0, #21
  177. bx lr
  178. .size _get_frame, . - _get_frame
  179. .thumb_func
  180. .type _enable, %function
  181. _enable:
  182. ldr r2, =#RCC_BASE //RCC
  183. movs r3, #0x01
  184. lsls r3, #23 //USBEN or USBRST
  185. cbz r0, .L_disable
  186. .L_enable:
  187. /* enabling and resetting USB peripheral */
  188. ldr r1, =#USB_REGBASE
  189. ldr r0, [r2, #RCC_APB1ENR]
  190. orrs r0, r3
  191. str r0, [r2, #RCC_APB1ENR] //RCC->APB1ENR |= USBEN
  192. ldr r0, [r2, #RCC_APB1RSTR]
  193. orrs r0, r3
  194. str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR |= USBRST
  195. bics r0, r3
  196. str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR &= ~USBRST
  197. /* enabling SYSCFG peripheral */
  198. movs r3, #0x01 //SYSCFGEN
  199. ldr r0, [r2, #RCC_APB2ENR]
  200. orrs r0, r3
  201. str r0, [r2, #RCC_APB2ENR]
  202. /* setting up USB CNTR */
  203. #if !defined(USBD_SOF_DISABLED)
  204. movs r0, #0xBE // CTRM | ERRM | WKUPM | SUSPM | RESETM | SOFM
  205. #else
  206. movs r0, #0xBC // CTRM | ERRM | WKUPM | SUSPM | RESETM
  207. #endif
  208. lsls r0, #0x08
  209. strh r0, [r1, #USB_CNTR] //set USB->CNTR
  210. bx lr
  211. .L_disable:
  212. ldr r0, [r2, #RCC_APB1ENR]
  213. tst r0, r3
  214. beq .L_enable_end // usb is already disabled
  215. /* disabling USB peripheral */
  216. bics r0, r3
  217. str r0, [r2, #RCC_APB1ENR]
  218. /* disabling USB_PU in SYSCFG_PMC */
  219. movs r3, #0x01
  220. ldr r1, =#SYSCFG_BASE
  221. ldr r0, [r1, #SYSCFG_PMC]
  222. bics r0, r3
  223. str r0, [r1, #SYSCFG_PMC]
  224. bx lr
  225. .L_enable_end:
  226. bx lr
  227. .size _enable, . - _enable
  228. .thumb_func
  229. .type _ep_setstall, %function
  230. /*void ep_settall(uint8_t ep, bool stall)
  231. * in R0 <- endpoint number
  232. * in R1 <- 0 if unstall, !0 if stall
  233. */
  234. _ep_setstall:
  235. push {r4, lr}
  236. lsls r2, r0, #28
  237. lsrs r2, #26
  238. ldr r3, =#USB_EPBASE
  239. adds r3, r2 // epr -> r3
  240. movs r2, 0x30 // TX_STAT_MASK -> r2
  241. ldrh r4, [r3]
  242. lsls r4, #21
  243. lsrs r4, #29 // EP_TYPE | EP_KIND -> R4 LSB
  244. cmp r4, #0x04 // ISO ?
  245. beq .L_eps_exit
  246. cmp r0, #0x80
  247. blo .L_eps_rx
  248. .L_eps_tx:
  249. ldr r0, =#TX_STALL //stall TX
  250. cmp r1, #0x00
  251. bne .L_eps_reg_set
  252. .L_eps_tx_unstall:
  253. ldr r0, =#DTX_USTALL //unstall dblbulk or iso TX (VALID and clr DTOG_TX & SWBUF_TX)
  254. cmp r4, #0x01 // if doublebuffered bulk endpoint
  255. beq .L_eps_reg_set
  256. ldr r0, =#TX_USTALL // unstall other TX (NAKED + clr DTOG_TX)
  257. b .L_eps_reg_set
  258. .L_eps_rx:
  259. lsls r2, #8 // RX_STAT_MASK -> R2
  260. ldr r0,=#RX_STALL //stall RX
  261. cmp r1, #0x00
  262. bne .L_eps_reg_set
  263. .L_eps_rx_unstall:
  264. ldr r0, =#DRX_USTALL //unstall dblbulk or iso (VALID. clr DTOG_RX set SWBUF_RX)
  265. cmp r4, #0x01 // if dblbulk
  266. beq .L_eps_reg_set
  267. ldr r0, =#RX_USTALL // unstall other RX (VALID + clr
  268. /* R0 - mask and toggle bits
  269. * R2 - mask for STAT bits
  270. * R3 - endpoint register pointer
  271. */
  272. .L_eps_reg_set:
  273. ldrh r1, [r3] // *epr -> r1
  274. ands r2, r1 // check if endpoint disabled
  275. beq .L_eps_exit // do nothing
  276. eors r1, r0
  277. lsrs r0, #16
  278. ands r1, r0
  279. strh r1, [r3]
  280. .L_eps_exit:
  281. pop {r4, pc}
  282. .size _ep_setstall, . - _ep_setstall
  283. .thumb_func
  284. .type _ep_isstalled, %function
  285. /* bool ep_isstalled(uint8t ep) */
  286. _ep_isstalled:
  287. ldr r1, =#USB_EPBASE
  288. lsls r2, r0, #28
  289. lsrs r2, #26
  290. ldr r1, [r1, r2]
  291. lsls r1, #17
  292. cmp r0, #0x80
  293. bhs .L_eis_check
  294. lsls r1, #8
  295. .L_eis_check:
  296. lsrs r1, r1, #28
  297. subs r1, #0x01
  298. subs r0, r1, #0x01
  299. sbcs r1, r1
  300. rsbs r0, r1, #0
  301. bx lr
  302. .size _ep_isstalled, . - _ep_isstalled
  303. .thumb_func
  304. .type _ep_read, %function
  305. /* int32_t _ep_read(uint8_t ep, void *buf, uint16_t blen)
  306. * in R0 <- endpoint
  307. * in R1 <- *buffer
  308. * in R2 <- length of the buffer
  309. * out length of the recieved data -> R0 or 0 on error
  310. */
  311. _ep_read:
  312. push {r4, r5, lr}
  313. ldr r3, =#USB_EPBASE
  314. ldr r4, =#USB_PMABASE
  315. lsls r0, #28
  316. lsrs r0, #26
  317. adds r3, r0 // *EPR -> R3
  318. lsls r0, #2
  319. adds r4, r0 // *EPT -> R4
  320. ldrh r5, [r3] // reading epr
  321. /* validating endpoint */
  322. movs r0, #0x37
  323. lsls r0, #0x08
  324. ands r0, r5
  325. lsrs r0, #0x08
  326. cmp r0, #0x34 // (OK) RX_VALID + ISO
  327. beq .L_epr_iso
  328. cmp r0, #0x31 // (OK) RX_VALID + DBLBULK
  329. beq .L_epr_dbl
  330. cmp r0, #0x20 // (OK) RX_NAKED + BULK
  331. beq .L_epr_sngl
  332. cmp r0, #0x22 // (OK) RX_NAKED + CTRL
  333. beq .L_epr_sngl
  334. cmp r0, #0x26 // (OK) RX_NAKED + INTR
  335. beq .L_epr_sngl
  336. movs r0, #0xFF // endpoint contains no valid data
  337. sxtb r0, r0
  338. b .L_epr_exit
  339. /* processing */
  340. .L_epr_dbl:
  341. lsrs r0, r5, #8
  342. eors r0, r5
  343. lsrs r0, #7 // SW_RX ^ DTOG_RX -> CF
  344. bcs .L_epr_notog // jmp if SW_RX != DTOG_RX (VALID)
  345. ldr r0, =#EP_NOTOG
  346. ands r5, r0
  347. adds r5, #EP_RX_SWBUF
  348. strh r5, [r3] // toggling SW_RX
  349. .L_epr_notog:
  350. ldrh r5, [r3]
  351. lsls r5, #8 // shift SW_RX to DTOG_RX
  352. .L_epr_iso:
  353. lsrs r5, #15 // DTOG_RX -> CF
  354. bcs .L_epr_sngl
  355. subs r4, #0x08 // set RXADDR0
  356. .L_epr_sngl:
  357. ldrh r0, [r4, #RXCOUNT]
  358. lsrs r5, r0, #0x0A
  359. lsls r5, #0x0A // r5 = r5 & ~0x03FF
  360. strh r5, [r4, #RXCOUNT]
  361. lsls r0, #22
  362. lsrs r0, #22 // r0 &= 0x3FF (RX count)
  363. ldrh r5, [r4, #RXADDR]
  364. ldr r4, =#USB_PMABASE
  365. lsls r5, #0x01
  366. adds r5, r4 // R5 now has a physical address
  367. cmp r2, r0
  368. blo .L_epr_read
  369. mov r2, r0 // if buffer is larger
  370. .L_epr_read:
  371. cmp r2, #1
  372. blo .L_epr_read_end
  373. ldrh r4, [r5]
  374. strb r4, [r1]
  375. beq .L_epr_read_end
  376. lsrs r4, #8
  377. strb r4, [r1, #1]
  378. adds r1, #2
  379. adds r5, #4
  380. subs r2, #2
  381. bhi .L_epr_read
  382. .L_epr_read_end:
  383. ldrh r5, [r3] // reload EPR
  384. lsls r1, r5, #21
  385. lsrs r1, #29
  386. cmp r1, #0x04
  387. beq .L_epr_exit // ep is iso. no needs to set it to valid
  388. cmp r1, #0x01
  389. beq .L_epr_exit // ep is dblbulk. no needs to set it to valid
  390. ldr r2, =#TGL_SET(EP_RX_STAT , EP_RX_VAL)
  391. eors r5, r2
  392. lsrs r2, #16
  393. ands r5, r2
  394. strh r5, [r3] // set ep to VALID state
  395. .L_epr_exit:
  396. pop {r4, r5, pc}
  397. .size _ep_read, . - _ep_read
  398. .thumb_func
  399. .type _ep_write, %function
  400. /* int32_t ep_write(uint8_t ep, void *buf, uint16_t blen)
  401. * R0 -> endpoint
  402. * R1 -> *buffer
  403. * R2 -> data length
  404. * result -> R0
  405. */
  406. _ep_write:
  407. push {r4, r5, r6, lr}
  408. ldr r3, =#USB_EPBASE
  409. ldr r4, =#USB_PMABASE
  410. lsls r0, #28
  411. lsrs r0, #26
  412. adds r3, r0 // *EPR -> R3
  413. lsls r0, #2
  414. adds r4, r0 // TXADDR0 -> R4
  415. ldrh r5, [r3] // reading epr
  416. movs r0, #0x73
  417. lsls r0, #4
  418. ands r0, r5
  419. lsrs r0, #4
  420. cmp r0, #0x43 // (OK) TX_VALID + ISO
  421. beq .L_epw_iso
  422. cmp r0, #0x12 // (OK) TX_NAK + DBLBULK
  423. beq .L_epw_dbl
  424. cmp r0, #0x02 // (OK) TX_NAK + BULK
  425. beq .L_epw_sngl
  426. cmp r0, #0x22 // (OK) TX_NAK + CONTROL
  427. beq .L_epw_sngl
  428. cmp r0, #0x62 // (OK) TX_NAK + INTERRUPT
  429. beq .L_epw_sngl
  430. movs r0, #0xFF
  431. sxtb r0, r0
  432. b .L_epw_exit
  433. .L_epw_dbl:
  434. mvns r5, r5
  435. lsrs r5, #8 // ~SWBUF_TX -> DTOG_TX
  436. .L_epw_iso:
  437. lsrs r5, #7 // DTOG_TX -> CF
  438. bcs .L_epw_sngl
  439. adds r4, #8 // TXADDR1 -> R4
  440. .L_epw_sngl:
  441. strh r2, [r4, #TXCOUNT]
  442. mov r0, r2 // save count for return
  443. ldrh r5, [r4, #TXADDR]
  444. ldr r4, =#USB_PMABASE
  445. lsls r5, #1
  446. adds r5, r4 // PMA BUFFER -> R5
  447. .L_epw_write:
  448. cmp r2, #1
  449. blo .L_epw_write_end
  450. ldrb r4, [r1]
  451. beq .L_epw_store
  452. ldrb r6, [r1, #1]
  453. lsls r6, #8
  454. orrs r4, r6
  455. .L_epw_store:
  456. strh r4, [r5]
  457. adds r5, #4
  458. adds r1, #2
  459. subs r2, #2
  460. bhi .L_epw_write
  461. .L_epw_write_end:
  462. ldrh r5, [r3] // reload EPR
  463. lsls r1, r5, #21
  464. lsrs r1, #29
  465. cmp r1, #0x04
  466. beq .L_epw_exit // isochronous ep. do nothing
  467. ldr r2, =#TGL_SET(EP_TX_STAT, EP_TX_VAL)
  468. cmp r1, #0x01
  469. bne .L_epw_setstate // NOT a doublebuffered bulk
  470. ldr r2, =#TGL_SET(EP_TX_SWBUF, EP_TX_SWBUF)
  471. bics r5, r2 // clear TX_SWBUF
  472. .L_epw_setstate:
  473. eors r5, r2
  474. lsrs r2, #16
  475. ands r5, r2
  476. strh r5, [r3]
  477. .L_epw_exit:
  478. pop {r4, r5, r6, pc}
  479. .size _ep_write, .- _ep_write
  480. /* internal function */
  481. /* requester size passed in R2 */
  482. /* result returns in R0 CF=1 if OK*/
  483. _get_next_pma:
  484. push {r1, r3, r4, lr}
  485. movs r1, #16
  486. movs r3, #1
  487. lsls r3, #9 //R3 MAX_PMA_SIZE 512b
  488. ldr r0, =#USB_PMABASE
  489. .L_gnp_chkaddr:
  490. ldrh r4, [r0, #0] //txaddr
  491. tst r4, r4
  492. beq .L_gnp_nxtaddr
  493. cmp r3, r4
  494. blo .L_gnp_nxtaddr
  495. mov r3, r4
  496. .L_gnp_nxtaddr:
  497. adds r0, #8
  498. subs r1, #1
  499. bne .L_gnp_chkaddr
  500. subs r0, r3, r2
  501. blo .L_gnp_exit
  502. cmp r0, #0x40 //check for the pma table overlap
  503. .L_gnp_exit:
  504. pop {r1, r3, r4, pc}
  505. .size _get_next_pma, . - _get_next_pma
  506. .thumb_func
  507. .type _ep_config, %function
  508. /* bool ep_config(uint8_t ep, uint8_t eptype, uint16_t epsize)
  509. * R0 <- ep
  510. * R1 <- eptype
  511. * R2 <- epsize
  512. * result -> R0
  513. */
  514. _ep_config:
  515. push {r4, r5, lr}
  516. movs r3, 0x01
  517. ands r3, r2
  518. adds r2, r3 //R2 -> halfword aligned epsize
  519. movs r3, #0x00 //BULK
  520. cmp r1, #0x02 // is eptype bulk ?
  521. beq .L_epc_settype
  522. movs r3, #0x01 //DBLBULK
  523. cmp r1, #0x06
  524. beq .L_epc_settype
  525. movs r3, #0x02 //CONTROL
  526. cmp r1, #0x00
  527. beq .L_epc_settype
  528. movs r3, #0x04 //ISO
  529. cmp r1, #0x01
  530. beq .L_epc_settype
  531. movs r3, #0x06 //INTERRUPT
  532. .L_epc_settype:
  533. lsls r3, #8
  534. lsls r4, r0, #28
  535. lsrs r4, #28
  536. orrs r3, r4
  537. lsls r4, #2
  538. ldr r5, =#USB_EPBASE
  539. strh r3, [r5, r4] //setup EPTYPE EPKIND EPADDR
  540. cmp r1, #0x00 // is a control ep ?
  541. beq .L_epc_setuptx
  542. cmp r0, #0x80
  543. blo .L_epc_setuprx
  544. .L_epc_setuptx:
  545. ldr r5, =#USB_PMABASE
  546. lsls r4, #2
  547. adds r5, r4
  548. bl _get_next_pma
  549. bcc .L_epc_fail
  550. strh r0, [r5, #TXADDR] //store txaddr or txaddr0
  551. movs r0, #0x00
  552. strh r0, [r5, #TXCOUNT] //store txcnt
  553. cmp r1, #0x06 // is DBLBULK
  554. beq .L_epc_txdbl
  555. ldr r3, =#TX_USTALL //set state NAKED , clr DTOG_TX
  556. cmp r1, #0x01 // is ISO
  557. bne .L_epc_txsetstate //
  558. .L_epc_txdbl:
  559. ldr r3, =#DTX_USTALL //set state VALID clr DTOG_TX & SWBUF_TX
  560. bl _get_next_pma
  561. bcc .L_epc_fail
  562. strh r0, [r5, #TXADDR1] //store txaddr1
  563. movs r0, #0x00
  564. strh r0, [r5, #TXCOUNT1] //store txcnt
  565. .L_epc_txsetstate:
  566. ldr r5, =#USB_EPBASE
  567. lsrs r4, #2
  568. ldrh r0, [r5, r4]
  569. eors r0, r3
  570. lsrs r3, #16
  571. ands r0, r3
  572. strh r0, [r5, r4]
  573. cmp r1, #0x00 //is a control ep ?
  574. bne .L_epc_exit
  575. .L_epc_setuprx:
  576. mov r3, r2
  577. cmp r2, #62
  578. bls .L_epc_rxbb
  579. movs r3, #0x1F
  580. ands r3, r2
  581. bne .L_epc_rxaa
  582. subs r2, #0x20
  583. .L_epc_rxaa:
  584. bics r2, r3
  585. lsrs r3, r2, #4
  586. adds r3, #0x40
  587. adds r2, #0x20
  588. .L_epc_rxbb:
  589. lsls r3, #9
  590. ldr r5, =#USB_PMABASE
  591. lsls r4, #2
  592. adds r5, r4
  593. /* RX or RX1 */
  594. bl _get_next_pma
  595. bcc .L_epc_fail
  596. strh r0, [r5, #RXADDR]
  597. strh r3, [r5, #RXCOUNT]
  598. ldr r0, =#RX_USTALL
  599. /* check if doublebuffered */
  600. cmp r1, 0x06 //if dblbulk
  601. beq .L_epc_rxdbl
  602. cmp r1, 0x01 // iso
  603. bne .L_epc_rxsetstate
  604. .L_epc_rxdbl:
  605. bl _get_next_pma
  606. bcc .L_epc_fail
  607. strh r0, [r5, #RXADDR0] //store rxaddr0
  608. strh r3, [r5, #RXCOUNT0] //store rxcnt0
  609. ldr r0, =#DRX_USTALL
  610. .L_epc_rxsetstate:
  611. ldr r5, =#USB_EPBASE
  612. lsrs r4, #2
  613. ldrh r3, [r5, r4]
  614. eors r3, r0
  615. lsrs r0, #16
  616. ands r3, r0
  617. strh r3, [r5, r4]
  618. .L_epc_exit:
  619. movs r0, #0x01
  620. pop {r4, r5, pc}
  621. .L_epc_fail:
  622. movs r0, #0x00
  623. pop {r4, r5, pc}
  624. .size _ep_config, . - _ep_config
  625. .thumb_func
  626. .type _ep_deconfig, %function
  627. /* void ep_deconfig( uint8_t ep)
  628. * R0 <- ep
  629. */
  630. _ep_deconfig:
  631. lsls r1, r0, #28
  632. lsrs r1, #26
  633. ldr r2, =#USB_EPBASE
  634. ldr r3, =#USB_PMABASE
  635. adds r2, r1
  636. lsls r1, #1
  637. adds r3, r1
  638. /* clearing endpoint register */
  639. ldr r1, =#EP_NOTOG
  640. ldrh r0, [r2]
  641. bics r0, r1
  642. strh r0, [r2]
  643. /* clearing PMA data */
  644. movs r0, #0x00
  645. strh r0, [r3, #TXADDR]
  646. strh r0, [r3, #TXCOUNT]
  647. strh r0, [r3, #RXADDR]
  648. strh r0, [r3, #RXCOUNT]
  649. bx lr
  650. .size _ep_deconfig, . - _ep_config
  651. #define ISTRSHIFT 8
  652. #define ISTRBIT(bit) ((1 << bit) >> ISTRSHIFT)
  653. .thumb_func
  654. .type _evt_poll, %function
  655. /*void evt_poll(usbd_device *dev, usbd_evt_callback callback)*/
  656. _evt_poll:
  657. push {r0, r1, r4, r5}
  658. ldr r3, =#USB_REGBASE
  659. ldrh r0, [r3, #4] //USB->ISTR -> R2
  660. /* ep_index -> R2 */
  661. movs r2, 0x07
  662. ands r2, r0
  663. /* checking USB->ISTR for events */
  664. #if !defined(USBD_SOF_DISABLED)
  665. lsrs r1, r0, #10 //SOFM -> CF
  666. bcs .L_ep_sofm
  667. #endif
  668. lsrs r1, r0, #11 //RESETM -> CF
  669. bcs .L_ep_resetm
  670. lsrs r1, r0, #16 //CTRM -> CF
  671. bcs .L_ep_ctrm
  672. lsrs r1, r0, #14 //ERRM -> CF
  673. bcs .L_ep_errm
  674. lsrs r1, r0, #13 //WKUPM -> CF
  675. bcs .L_ep_wkupm
  676. lsrs r1, r0, #12 //SUSPM -> CF
  677. bcs .L_ep_suspm
  678. /* exit with no callback */
  679. pop {r0, r1, r4 , r5}
  680. bx lr
  681. .L_ep_ctrm:
  682. movs r5, #0x80 // CTR_TX mask to R5
  683. ldr r0,=#USB_EPBASE
  684. lsrs r0, #2
  685. adds r0, r2
  686. lsls r0, #2 // R0 ep register address
  687. ldrh r4, [r0] // R4 EPR valur
  688. lsrs r3, r4, #8 // CTR_TX -> CF
  689. bcc .L_ep_ctr_rx
  690. /* CTR_TX event */
  691. movs r1, #usbd_evt_eptx
  692. orrs r2, r5 // set endpoint tx
  693. b .L_ep_clr_ctr
  694. .L_ep_ctr_rx:
  695. /* CTR_RX RX or SETUP */
  696. lsls r5, #0x08 // set mask to CRT_RX
  697. movs r1, #usbd_evt_eprx
  698. lsls r3, r4, #21 //SETUP -> CF
  699. bcc .L_ep_clr_ctr
  700. movs r1, #usbd_evt_epsetup
  701. .L_ep_clr_ctr:
  702. bics r4, r5 //clear CTR flag
  703. ldr r5, =#EP_NOTOG
  704. ands r4, r5
  705. strh r4, [r0] // store
  706. b .L_ep_callback
  707. .L_ep_errm:
  708. movs r1, #usbd_evt_error
  709. movs r4, #ISTRBIT(13)
  710. b .L_ep_clristr
  711. #if !defined(USBD_SOF_DISABLED)
  712. .L_ep_sofm:
  713. movs r1, #usbd_evt_sof
  714. movs r4, #ISTRBIT(9)
  715. b .L_ep_clristr
  716. #endif
  717. .L_ep_wkupm:
  718. ldrh r1, [r3, #0] //R1 USB->CNTR
  719. movs r5, #0x08
  720. bics r1, r5 //clr FSUSP
  721. strh r1, [r3, #0] //USB->CNTR R2
  722. movs r1, #usbd_evt_wkup
  723. movs r4, #ISTRBIT(12)
  724. b .L_ep_clristr
  725. .L_ep_suspm:
  726. ldrh r1, [r3, #0] //R1 USB->CNTR
  727. movs r5, #0x08
  728. orrs r1, r5 //set FSUSP
  729. strh r1, [r3, #0] //USB->CNTR R2
  730. movs r1, #usbd_evt_susp
  731. movs r4, #ISTRBIT(11)
  732. b .L_ep_clristr
  733. /* do reset routine */
  734. .L_ep_resetm:
  735. movs r1, #7
  736. ldr r2, =#USB_EPBASE
  737. ldr r0, =#USB_PMABASE
  738. ldr r5, =#EP_NOTOG
  739. .L_ep_reset_loop:
  740. ldrh r4, [r2]
  741. bics r4, r5
  742. strh r4, [r2]
  743. movs r4, #0
  744. strh r4, [r0, #TXADDR]
  745. strh r4, [r0, #TXCOUNT]
  746. strh r4, [r0, #RXADDR]
  747. strh r4, [r0, #RXCOUNT]
  748. adds r2, #0x04
  749. adds r0, #0x10
  750. subs r1, #1
  751. bpl .L_ep_reset_loop
  752. movs r2, #0x00
  753. strh r2, [r3, #0x10] // 0 -> USB->BTABLE
  754. movs r1, #usbd_evt_reset
  755. movs r4, #ISTRBIT(10)
  756. .L_ep_clristr:
  757. lsls r4, #ISTRSHIFT
  758. ldrh r0, [r3, #4]
  759. bics r0, r4
  760. strh r0, [r3, #4]
  761. .L_ep_callback:
  762. pop {r0, r3, r4, r5 }
  763. bx r3
  764. .size _evt_poll, . - _evt_poll
  765. .pool
  766. .end
  767. #endif