usbd_stm32l100_devfs_asm.S 21 KB

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  1. /* This file is the part of the Lightweight USB device Stack for STM32 microcontrollers
  2. *
  3. * Copyright ©2016 Dmitry Filimonchuk <dmitrystu[at]gmail[dot]com>
  4. *
  5. * Licensed under the Apache License, Version 2.0 (the "License");
  6. * you may not use this file except in compliance with the License.
  7. * You may obtain a copy of the License at
  8. * http://www.apache.org/licenses/LICENSE-2.0
  9. * Unless required by applicable law or agreed to in writing, software
  10. * distributed under the License is distributed on an "AS IS" BASIS,
  11. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. * See the License for the specific language governing permissions and
  13. * limitations under the License.
  14. */
  15. #if !defined (__ASSEMBLER__)
  16. #define __ASSEMBLER__
  17. #endif
  18. #include "usb.h"
  19. #if defined(USBD_STM32L100)
  20. #include "memmap.inc"
  21. #define EP_SETUP 0x0800
  22. #define EP_TYPE 0x0600
  23. #define EP_KIND 0x0100
  24. #define EP_ADDR 0x000F
  25. #define EP_RX_CTR 0x8000
  26. #define EP_RX_DTOG 0x4000
  27. #define EP_RX_STAT 0x3000
  28. #define EP_RX_SWBUF 0x0040
  29. #define EP_RX_DIS 0x0000
  30. #define EP_RX_STAL 0x1000
  31. #define EP_RX_NAK 0x2000
  32. #define EP_RX_VAL 0x3000
  33. #define EP_TX_CTR 0x0080
  34. #define EP_TX_DTOG 0x0040
  35. #define EP_TX_STAT 0x0030
  36. #define EP_TX_SWBUF 0x4000
  37. #define EP_TX_DIS 0x0000
  38. #define EP_TX_STAL 0x0010
  39. #define EP_TX_NAK 0x0020
  40. #define EP_TX_VAL 0x0030
  41. #define RXADDR0 0x00
  42. #define RXCOUNT0 0x04
  43. #define RXADDR1 0x08
  44. #define RXCOUNT1 0x0C
  45. #define TXADDR0 0x00
  46. #define TXCOUNT0 0x04
  47. #define TXADDR1 0x08
  48. #define TXCOUNT1 0x0C
  49. #define TXADDR 0x00
  50. #define TXCOUNT 0x04
  51. #define RXADDR 0x08
  52. #define RXCOUNT 0x0C
  53. #define EP_NOTOG (EP_RX_CTR | EP_TX_CTR | EP_SETUP | EP_TYPE | EP_KIND | EP_ADDR)
  54. #define TGL_SET(mask, bits) ((EP_NOTOG | (mask))<<16 | (bits))
  55. #define TX_STALL TGL_SET(EP_TX_STAT, EP_TX_STAL)
  56. #define RX_STALL TGL_SET(EP_RX_STAT, EP_RX_STAL)
  57. #define TX_USTALL TGL_SET(EP_TX_STAT | EP_TX_DTOG, EP_TX_NAK)
  58. #define RX_USTALL TGL_SET(EP_RX_STAT | EP_RX_DTOG, EP_RX_VAL)
  59. #define DTX_USTALL TGL_SET(EP_TX_STAT | EP_TX_DTOG | EP_TX_SWBUF, EP_TX_VAL)
  60. #define DRX_USTALL TGL_SET(EP_RX_STAT | EP_RX_DTOG | EP_RX_SWBUF, EP_RX_VAL | EP_RX_SWBUF)
  61. .syntax unified
  62. .cpu cortex-m3
  63. .text
  64. .thumb
  65. .globl usbd_devfs_asm
  66. .align 2
  67. usbd_devfs_asm:
  68. .long 0
  69. .long _enable
  70. .long _connect
  71. .long _setaddr
  72. .long _ep_config
  73. .long _ep_deconfig
  74. .long _ep_read
  75. .long _ep_write
  76. .long _ep_setstall
  77. .long _ep_isstalled
  78. .long _evt_poll
  79. .long _get_frame
  80. .long _get_serial_desc
  81. .size usbd_devfs_asm, . - usbd_devfs_asm
  82. .thumb_func
  83. .type _get_serial_desc, %function
  84. /* uint16_t get_serial_desc (void *buffer)
  85. * R0 <- buffer for the string descriptor
  86. * descrpitor size -> R0
  87. */
  88. _get_serial_desc:
  89. push {r4, r5, lr}
  90. movs r1, #18 //descriptor size 18 bytes
  91. strb r1, [r0]
  92. movs r1, #0x03 //DTYPE_STRING
  93. strb r1, [r0, #0x01]
  94. ldr r5, .L_uid_base //UID3 this is the serial number
  95. ldr r4, .L_fnv1a_offset //FNV1A offset
  96. ldr r2, [r5, 0x00] //UID0
  97. bl .L_fnv1a
  98. ldr r2, [r5, 0x04] //UID1
  99. bl .L_fnv1a
  100. ldr r2, [r5, 0x14] //UID2
  101. bl .L_fnv1a
  102. movs r3, #28
  103. .L_gsn_loop:
  104. lsrs r1, r4, r3
  105. and r1, #0x0F
  106. cmp r1, #0x09
  107. ite gt
  108. addgt r1, #55
  109. addle r1, #48
  110. .L_gsn_store:
  111. adds r0, #0x02
  112. strb r1, [r0]
  113. lsrs r1, #0x08
  114. strb r1, [r0, #0x01]
  115. subs r3, #0x04
  116. bpl .L_gsn_loop
  117. movs r0, #18
  118. pop {r4, r5, pc}
  119. .L_fnv1a:
  120. movs r3, #0x04
  121. .L_fnv1a_loop:
  122. uxtb r1, r2
  123. eors r4, r1
  124. ldr r1, .L_fnv1a_prime //FNV1A prime
  125. muls r4, r1
  126. lsrs r2, #0x08
  127. subs r3, #0x01
  128. bne .L_fnv1a_loop
  129. bx lr
  130. .align 2
  131. .L_uid_base: .long UID_BASE
  132. .L_fnv1a_offset: .long 2166136261
  133. .L_fnv1a_prime: .long 16777619
  134. .size _get_serial_desc, . - _get_serial_desc
  135. .thumb_func
  136. .type _connect, %function
  137. _connect:
  138. ldr r1, =#SYSCFG_BASE
  139. movs r3, #0x01
  140. ldr r2, [r1, #SYSCFG_PMC]
  141. bics r2, r3
  142. cbz r0, .L_conn_store
  143. orrs r2, r3
  144. .L_conn_store:
  145. str r2, [r1, #SYSCFG_PMC]
  146. movs r0, #usbd_lane_unk
  147. bx lr
  148. .size _connect, . - _connect
  149. .thumb_func
  150. .type _setaddr, %function
  151. _setaddr:
  152. ldr r1, =USB_REGBASE
  153. adds r0, #0x80
  154. strh r0, [r1, #USB_DADDR] //USB->DADDR
  155. bx lr
  156. .size _setaddr, . - _setaddr
  157. .thumb_func
  158. .type _get_frame, %function
  159. _get_frame:
  160. ldr r0, =#USB_REGBASE
  161. ldrh r0, [r0, #USB_FNR] //FNR
  162. lsls r0, #21
  163. lsrs r0, #21
  164. bx lr
  165. .size _get_frame, . - _get_frame
  166. .thumb_func
  167. .type _enable, %function
  168. _enable:
  169. ldr r2, =#RCC_BASE //RCC
  170. movs r3, #0x01
  171. lsls r3, #23 //USBEN or USBRST
  172. cbz r0, .L_disable
  173. .L_enable:
  174. /* enabling and resetting USB peripheral */
  175. ldr r1, =#USB_REGBASE
  176. ldr r0, [r2, #RCC_APB1ENR]
  177. orrs r0, r3
  178. str r0, [r2, #RCC_APB1ENR] //RCC->APB1ENR |= USBEN
  179. ldr r0, [r2, #RCC_APB1RSTR]
  180. orrs r0, r3
  181. str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR |= USBRST
  182. bics r0, r3
  183. str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR &= ~USBRST
  184. /* enabling SYSCFG peripheral */
  185. movs r3, #0x01 //SYSCFGEN
  186. ldr r0, [r2, #RCC_APB2ENR]
  187. orrs r0, r3
  188. str r0, [r2, #RCC_APB2ENR]
  189. /* setting up USB CNTR */
  190. #if !defined(USBD_SOF_DISABLED)
  191. movs r0, #0xBE // CTRM | ERRM | WKUPM | SUSPM | RESETM | SOFM
  192. #else
  193. movs r0, #0xBC // CTRM | ERRM | WKUPM | SUSPM | RESETM
  194. #endif
  195. lsls r0, #0x08
  196. strh r0, [r1, #USB_CNTR] //set USB->CNTR
  197. bx lr
  198. .L_disable:
  199. ldr r0, [r2, #RCC_APB1ENR]
  200. tst r0, r3
  201. beq .L_enable_end // usb is already disabled
  202. /* disabling USB peripheral */
  203. bics r0, r3
  204. str r0, [r2, #RCC_APB1ENR]
  205. /* disabling USB_PU in SYSCFG_PMC */
  206. movs r3, #0x01
  207. ldr r1, =#SYSCFG_BASE
  208. ldr r0, [r1, #SYSCFG_PMC]
  209. bics r0, r3
  210. str r0, [r1, #SYSCFG_PMC]
  211. bx lr
  212. .L_enable_end:
  213. bx lr
  214. .size _enable, . - _enable
  215. .thumb_func
  216. .type _ep_setstall, %function
  217. /*void ep_settall(uint8_t ep, bool stall)
  218. * in R0 <- endpoint number
  219. * in R1 <- 0 if unstall, !0 if stall
  220. */
  221. _ep_setstall:
  222. push {r4, lr}
  223. lsls r2, r0, #28
  224. lsrs r2, #26
  225. ldr r3, =#USB_EPBASE
  226. adds r3, r2 // epr -> r3
  227. movs r2, 0x30 // TX_STAT_MASK -> r2
  228. ldrh r4, [r3]
  229. lsls r4, #21
  230. lsrs r4, #29 // EP_TYPE | EP_KIND -> R4 LSB
  231. cmp r4, #0x04 // ISO ?
  232. beq .L_eps_exit
  233. cmp r0, #0x80
  234. blo .L_eps_rx
  235. .L_eps_tx:
  236. ldr r0, =#TX_STALL //stall TX
  237. cmp r1, #0x00
  238. bne .L_eps_reg_set
  239. .L_eps_tx_unstall:
  240. ldr r0, =#DTX_USTALL //unstall dblbulk or iso TX (VALID and clr DTOG_TX & SWBUF_TX)
  241. cmp r4, #0x01 // if doublebuffered bulk endpoint
  242. beq .L_eps_reg_set
  243. ldr r0, =#TX_USTALL // unstall other TX (NAKED + clr DTOG_TX)
  244. b .L_eps_reg_set
  245. .L_eps_rx:
  246. lsls r2, #8 // RX_STAT_MASK -> R2
  247. ldr r0,=#RX_STALL //stall RX
  248. cmp r1, #0x00
  249. bne .L_eps_reg_set
  250. .L_eps_rx_unstall:
  251. ldr r0, =#DRX_USTALL //unstall dblbulk or iso (VALID. clr DTOG_RX set SWBUF_RX)
  252. cmp r4, #0x01 // if dblbulk
  253. beq .L_eps_reg_set
  254. ldr r0, =#RX_USTALL // unstall other RX (VALID + clr
  255. /* R0 - mask and toggle bits
  256. * R2 - mask for STAT bits
  257. * R3 - endpoint register pointer
  258. */
  259. .L_eps_reg_set:
  260. ldrh r1, [r3] // *epr -> r1
  261. ands r2, r1 // check if endpoint disabled
  262. beq .L_eps_exit // do nothing
  263. eors r1, r0
  264. lsrs r0, #16
  265. ands r1, r0
  266. strh r1, [r3]
  267. .L_eps_exit:
  268. pop {r4, pc}
  269. .size _ep_setstall, . - _ep_setstall
  270. .thumb_func
  271. .type _ep_isstalled, %function
  272. /* bool ep_isstalled(uint8t ep) */
  273. _ep_isstalled:
  274. ldr r1, =#USB_EPBASE
  275. lsls r2, r0, #28
  276. lsrs r2, #26
  277. ldr r1, [r1, r2]
  278. lsls r1, #17
  279. cmp r0, #0x80
  280. bhs .L_eis_check
  281. lsls r1, #8
  282. .L_eis_check:
  283. lsrs r1, r1, #28
  284. subs r1, #0x01
  285. subs r0, r1, #0x01
  286. sbcs r1, r1
  287. rsbs r0, r1, #0
  288. bx lr
  289. .size _ep_isstalled, . - _ep_isstalled
  290. .thumb_func
  291. .type _ep_read, %function
  292. /* int32_t _ep_read(uint8_t ep, void *buf, uint16_t blen)
  293. * in R0 <- endpoint
  294. * in R1 <- *buffer
  295. * in R2 <- length of the buffer
  296. * out length of the recieved data -> R0 or 0 on error
  297. */
  298. _ep_read:
  299. push {r4, r5, lr}
  300. ldr r3, =#USB_EPBASE
  301. ldr r4, =#USB_PMABASE
  302. lsls r0, #28
  303. lsrs r0, #26
  304. adds r3, r0 // *EPR -> R3
  305. lsls r0, #2
  306. adds r4, r0 // *EPT -> R4
  307. ldrh r5, [r3] // reading epr
  308. /* validating endpoint */
  309. movs r0, #0x37
  310. lsls r0, #0x08
  311. ands r0, r5
  312. lsrs r0, #0x08
  313. cmp r0, #0x34 // (OK) RX_VALID + ISO
  314. beq .L_epr_iso
  315. cmp r0, #0x31 // (OK) RX_VALID + DBLBULK
  316. beq .L_epr_dbl
  317. cmp r0, #0x20 // (OK) RX_NAKED + BULK
  318. beq .L_epr_sngl
  319. cmp r0, #0x22 // (OK) RX_NAKED + CTRL
  320. beq .L_epr_sngl
  321. cmp r0, #0x26 // (OK) RX_NAKED + INTR
  322. beq .L_epr_sngl
  323. movs r0, #0xFF // endpoint contains no valid data
  324. sxtb r0, r0
  325. b .L_epr_exit
  326. /* processing */
  327. .L_epr_dbl:
  328. lsrs r0, r5, #8
  329. eors r0, r5
  330. lsrs r0, #7 // SW_RX ^ DTOG_RX -> CF
  331. bcs .L_epr_notog // jmp if SW_RX != DTOG_RX (VALID)
  332. ldr r0, =#EP_NOTOG
  333. ands r5, r0
  334. adds r5, #EP_RX_SWBUF
  335. strh r5, [r3] // toggling SW_RX
  336. .L_epr_notog:
  337. ldrh r5, [r3]
  338. lsls r5, #8 // shift SW_RX to DTOG_RX
  339. .L_epr_iso:
  340. lsrs r5, #15 // DTOG_RX -> CF
  341. bcs .L_epr_sngl
  342. subs r4, #0x08 // set RXADDR0
  343. .L_epr_sngl:
  344. ldrh r0, [r4, #RXCOUNT]
  345. lsrs r5, r0, #0x0A
  346. lsls r5, #0x0A // r5 = r5 & ~0x03FF
  347. strh r5, [r4, #RXCOUNT]
  348. lsls r0, #22
  349. lsrs r0, #22 // r0 &= 0x3FF (RX count)
  350. ldrh r5, [r4, #RXADDR]
  351. ldr r4, =#USB_PMABASE
  352. lsls r5, #0x01
  353. adds r5, r4 // R5 now has a physical address
  354. cmp r2, r0
  355. blo .L_epr_read
  356. mov r2, r0 // if buffer is larger
  357. .L_epr_read:
  358. cmp r2, #1
  359. blo .L_epr_read_end
  360. ldrh r4, [r5]
  361. strb r4, [r1]
  362. beq .L_epr_read_end
  363. lsrs r4, #8
  364. strb r4, [r1, #1]
  365. adds r1, #2
  366. adds r5, #4
  367. subs r2, #2
  368. bhi .L_epr_read
  369. .L_epr_read_end:
  370. ldrh r5, [r3] // reload EPR
  371. lsls r1, r5, #21
  372. lsrs r1, #29
  373. cmp r1, #0x04
  374. beq .L_epr_exit // ep is iso. no needs to set it to valid
  375. cmp r1, #0x01
  376. beq .L_epr_exit // ep is dblbulk. no needs to set it to valid
  377. ldr r2, =#TGL_SET(EP_RX_STAT , EP_RX_VAL)
  378. eors r5, r2
  379. lsrs r2, #16
  380. ands r5, r2
  381. strh r5, [r3] // set ep to VALID state
  382. .L_epr_exit:
  383. pop {r4, r5, pc}
  384. .size _ep_read, . - _ep_read
  385. .thumb_func
  386. .type _ep_write, %function
  387. /* int32_t ep_write(uint8_t ep, void *buf, uint16_t blen)
  388. * R0 -> endpoint
  389. * R1 -> *buffer
  390. * R2 -> data length
  391. * result -> R0
  392. */
  393. _ep_write:
  394. push {r4, r5, r6, lr}
  395. ldr r3, =#USB_EPBASE
  396. ldr r4, =#USB_PMABASE
  397. lsls r0, #28
  398. lsrs r0, #26
  399. adds r3, r0 // *EPR -> R3
  400. lsls r0, #2
  401. adds r4, r0 // TXADDR0 -> R4
  402. ldrh r5, [r3] // reading epr
  403. movs r0, #0x73
  404. lsls r0, #4
  405. ands r0, r5
  406. lsrs r0, #4
  407. cmp r0, #0x43 // (OK) TX_VALID + ISO
  408. beq .L_epw_iso
  409. cmp r0, #0x12 // (OK) TX_NAK + DBLBULK
  410. beq .L_epw_dbl
  411. cmp r0, #0x02 // (OK) TX_NAK + BULK
  412. beq .L_epw_sngl
  413. cmp r0, #0x22 // (OK) TX_NAK + CONTROL
  414. beq .L_epw_sngl
  415. cmp r0, #0x62 // (OK) TX_NAK + INTERRUPT
  416. beq .L_epw_sngl
  417. movs r0, #0xFF
  418. sxtb r0, r0
  419. b .L_epw_exit
  420. .L_epw_dbl:
  421. mvns r5, r5
  422. lsrs r5, #8 // ~SWBUF_TX -> DTOG_TX
  423. .L_epw_iso:
  424. lsrs r5, #7 // DTOG_TX -> CF
  425. bcs .L_epw_sngl
  426. adds r4, #8 // TXADDR1 -> R4
  427. .L_epw_sngl:
  428. strh r2, [r4, #TXCOUNT]
  429. mov r0, r2 // save count for return
  430. ldrh r5, [r4, #TXADDR]
  431. ldr r4, =#USB_PMABASE
  432. lsls r5, #1
  433. adds r5, r4 // PMA BUFFER -> R5
  434. .L_epw_write:
  435. cmp r2, #1
  436. blo .L_epw_write_end
  437. ldrb r4, [r1]
  438. beq .L_epw_store
  439. ldrb r6, [r1, #1]
  440. lsls r6, #8
  441. orrs r4, r6
  442. .L_epw_store:
  443. strh r4, [r5]
  444. adds r5, #4
  445. adds r1, #2
  446. subs r2, #2
  447. bhi .L_epw_write
  448. .L_epw_write_end:
  449. ldrh r5, [r3] // reload EPR
  450. lsls r1, r5, #21
  451. lsrs r1, #29
  452. cmp r1, #0x04
  453. beq .L_epw_exit // isochronous ep. do nothing
  454. ldr r2, =#TGL_SET(EP_TX_STAT, EP_TX_VAL)
  455. cmp r1, #0x01
  456. bne .L_epw_setstate // NOT a doublebuffered bulk
  457. ldr r2, =#TGL_SET(EP_TX_SWBUF, EP_TX_SWBUF)
  458. bics r5, r2 // clear TX_SWBUF
  459. .L_epw_setstate:
  460. eors r5, r2
  461. lsrs r2, #16
  462. ands r5, r2
  463. strh r5, [r3]
  464. .L_epw_exit:
  465. pop {r4, r5, r6, pc}
  466. .size _ep_write, .- _ep_write
  467. /* internal function */
  468. /* requester size passed in R2 */
  469. /* result returns in R0 CF=1 if OK*/
  470. _get_next_pma:
  471. push {r1, r3, r4, lr}
  472. movs r1, #16
  473. movs r3, #1
  474. lsls r3, #9 //R3 MAX_PMA_SIZE 512b
  475. ldr r0, =#USB_PMABASE
  476. .L_gnp_chkaddr:
  477. ldrh r4, [r0, #0] //txaddr
  478. tst r4, r4
  479. beq .L_gnp_nxtaddr
  480. cmp r3, r4
  481. blo .L_gnp_nxtaddr
  482. mov r3, r4
  483. .L_gnp_nxtaddr:
  484. adds r0, #8
  485. subs r1, #1
  486. bne .L_gnp_chkaddr
  487. subs r0, r3, r2
  488. blo .L_gnp_exit
  489. cmp r0, #0x40 //check for the pma table overlap
  490. .L_gnp_exit:
  491. pop {r1, r3, r4, pc}
  492. .size _get_next_pma, . - _get_next_pma
  493. .thumb_func
  494. .type _ep_config, %function
  495. /* bool ep_config(uint8_t ep, uint8_t eptype, uint16_t epsize)
  496. * R0 <- ep
  497. * R1 <- eptype
  498. * R2 <- epsize
  499. * result -> R0
  500. */
  501. _ep_config:
  502. push {r4, r5, lr}
  503. movs r3, 0x01
  504. ands r3, r2
  505. adds r2, r3 //R2 -> halfword aligned epsize
  506. movs r3, #0x00 //BULK
  507. cmp r1, #0x02 // is eptype bulk ?
  508. beq .L_epc_settype
  509. movs r3, #0x01 //DBLBULK
  510. cmp r1, #0x06
  511. beq .L_epc_settype
  512. movs r3, #0x02 //CONTROL
  513. cmp r1, #0x00
  514. beq .L_epc_settype
  515. movs r3, #0x04 //ISO
  516. cmp r1, #0x01
  517. beq .L_epc_settype
  518. movs r3, #0x06 //INTERRUPT
  519. .L_epc_settype:
  520. lsls r3, #8
  521. lsls r4, r0, #28
  522. lsrs r4, #28
  523. orrs r3, r4
  524. lsls r4, #2
  525. ldr r5, =#USB_EPBASE
  526. strh r3, [r5, r4] //setup EPTYPE EPKIND EPADDR
  527. cmp r1, #0x00 // is a control ep ?
  528. beq .L_epc_setuptx
  529. cmp r0, #0x80
  530. blo .L_epc_setuprx
  531. .L_epc_setuptx:
  532. ldr r5, =#USB_PMABASE
  533. lsls r4, #2
  534. adds r5, r4
  535. bl _get_next_pma
  536. bcc .L_epc_fail
  537. strh r0, [r5, #TXADDR] //store txaddr or txaddr0
  538. movs r0, #0x00
  539. strh r0, [r5, #TXCOUNT] //store txcnt
  540. cmp r1, #0x06 // is DBLBULK
  541. beq .L_epc_txdbl
  542. ldr r3, =#TX_USTALL //set state NAKED , clr DTOG_TX
  543. cmp r1, #0x01 // is ISO
  544. bne .L_epc_txsetstate //
  545. .L_epc_txdbl:
  546. ldr r3, =#DTX_USTALL //set state VALID clr DTOG_TX & SWBUF_TX
  547. bl _get_next_pma
  548. bcc .L_epc_fail
  549. strh r0, [r5, #TXADDR1] //store txaddr1
  550. movs r0, #0x00
  551. strh r0, [r5, #TXCOUNT1] //store txcnt
  552. .L_epc_txsetstate:
  553. ldr r5, =#USB_EPBASE
  554. lsrs r4, #2
  555. ldrh r0, [r5, r4]
  556. eors r0, r3
  557. lsrs r3, #16
  558. ands r0, r3
  559. strh r0, [r5, r4]
  560. cmp r1, #0x00 //is a control ep ?
  561. bne .L_epc_exit
  562. .L_epc_setuprx:
  563. mov r3, r2
  564. cmp r2, #62
  565. bls .L_epc_rxbb
  566. movs r3, #0x1F
  567. ands r3, r2
  568. bne .L_epc_rxaa
  569. subs r2, #0x20
  570. .L_epc_rxaa:
  571. bics r2, r3
  572. lsrs r3, r2, #4
  573. adds r3, #0x40
  574. adds r2, #0x20
  575. .L_epc_rxbb:
  576. lsls r3, #9
  577. ldr r5, =#USB_PMABASE
  578. lsls r4, #2
  579. adds r5, r4
  580. /* RX or RX1 */
  581. bl _get_next_pma
  582. bcc .L_epc_fail
  583. strh r0, [r5, #RXADDR]
  584. strh r3, [r5, #RXCOUNT]
  585. ldr r0, =#RX_USTALL
  586. /* check if doublebuffered */
  587. cmp r1, 0x06 //if dblbulk
  588. beq .L_epc_rxdbl
  589. cmp r1, 0x01 // iso
  590. bne .L_epc_rxsetstate
  591. .L_epc_rxdbl:
  592. bl _get_next_pma
  593. bcc .L_epc_fail
  594. strh r0, [r5, #RXADDR0] //store rxaddr0
  595. strh r3, [r5, #RXCOUNT0] //store rxcnt0
  596. ldr r0, =#DRX_USTALL
  597. .L_epc_rxsetstate:
  598. ldr r5, =#USB_EPBASE
  599. lsrs r4, #2
  600. ldrh r3, [r5, r4]
  601. eors r3, r0
  602. lsrs r0, #16
  603. ands r3, r0
  604. strh r3, [r5, r4]
  605. .L_epc_exit:
  606. movs r0, #0x01
  607. pop {r4, r5, pc}
  608. .L_epc_fail:
  609. movs r0, #0x00
  610. pop {r4, r5, pc}
  611. .size _ep_config, . - _ep_config
  612. .thumb_func
  613. .type _ep_deconfig, %function
  614. /* void ep_deconfig( uint8_t ep)
  615. * R0 <- ep
  616. */
  617. _ep_deconfig:
  618. lsls r1, r0, #28
  619. lsrs r1, #26
  620. ldr r2, =#USB_EPBASE
  621. ldr r3, =#USB_PMABASE
  622. adds r2, r1
  623. lsls r1, #1
  624. adds r3, r1
  625. /* clearing endpoint register */
  626. ldr r1, =#EP_NOTOG
  627. ldrh r0, [r2]
  628. bics r0, r1
  629. strh r0, [r2]
  630. /* clearing PMA data */
  631. movs r0, #0x00
  632. strh r0, [r3, #TXADDR]
  633. strh r0, [r3, #TXCOUNT]
  634. strh r0, [r3, #RXADDR]
  635. strh r0, [r3, #RXCOUNT]
  636. bx lr
  637. .size _ep_deconfig, . - _ep_config
  638. #define ISTRSHIFT 8
  639. #define ISTRBIT(bit) ((1 << bit) >> ISTRSHIFT)
  640. .thumb_func
  641. .type _evt_poll, %function
  642. /*void evt_poll(usbd_device *dev, usbd_evt_callback callback)*/
  643. _evt_poll:
  644. push {r0, r1, r4, r5}
  645. ldr r3, =#USB_REGBASE
  646. ldrh r0, [r3, #4] //USB->ISTR -> R2
  647. /* ep_index -> R2 */
  648. movs r2, 0x07
  649. ands r2, r0
  650. /* checking USB->ISTR for events */
  651. #if !defined(USBD_SOF_DISABLED)
  652. lsrs r1, r0, #10 //SOFM -> CF
  653. bcs .L_ep_sofm
  654. #endif
  655. lsrs r1, r0, #11 //RESETM -> CF
  656. bcs .L_ep_resetm
  657. lsrs r1, r0, #16 //CTRM -> CF
  658. bcs .L_ep_ctrm
  659. lsrs r1, r0, #14 //ERRM -> CF
  660. bcs .L_ep_errm
  661. lsrs r1, r0, #13 //WKUPM -> CF
  662. bcs .L_ep_wkupm
  663. lsrs r1, r0, #12 //SUSPM -> CF
  664. bcs .L_ep_suspm
  665. /* exit with no callback */
  666. pop {r0, r1, r4 , r5}
  667. bx lr
  668. .L_ep_ctrm:
  669. movs r5, #0x80 // CTR_TX mask to R5
  670. ldr r0,=#USB_EPBASE
  671. lsrs r0, #2
  672. adds r0, r2
  673. lsls r0, #2 // R0 ep register address
  674. ldrh r4, [r0] // R4 EPR valur
  675. lsrs r3, r4, #8 // CTR_TX -> CF
  676. bcc .L_ep_ctr_rx
  677. /* CTR_TX event */
  678. movs r1, #usbd_evt_eptx
  679. orrs r2, r5 // set endpoint tx
  680. b .L_ep_clr_ctr
  681. .L_ep_ctr_rx:
  682. /* CTR_RX RX or SETUP */
  683. lsls r5, #0x08 // set mask to CRT_RX
  684. movs r1, #usbd_evt_eprx
  685. lsls r3, r4, #21 //SETUP -> CF
  686. bcc .L_ep_clr_ctr
  687. movs r1, #usbd_evt_epsetup
  688. .L_ep_clr_ctr:
  689. bics r4, r5 //clear CTR flag
  690. ldr r5, =#EP_NOTOG
  691. ands r4, r5
  692. strh r4, [r0] // store
  693. b .L_ep_callback
  694. .L_ep_errm:
  695. movs r1, #usbd_evt_error
  696. movs r4, #ISTRBIT(13)
  697. b .L_ep_clristr
  698. #if !defined(USBD_SOF_DISABLED)
  699. .L_ep_sofm:
  700. movs r1, #usbd_evt_sof
  701. movs r4, #ISTRBIT(9)
  702. b .L_ep_clristr
  703. #endif
  704. .L_ep_wkupm:
  705. ldrh r1, [r3, #0] //R1 USB->CNTR
  706. movs r5, #0x08
  707. bics r1, r5 //clr FSUSP
  708. strh r1, [r3, #0] //USB->CNTR R2
  709. movs r1, #usbd_evt_wkup
  710. movs r4, #ISTRBIT(12)
  711. b .L_ep_clristr
  712. .L_ep_suspm:
  713. ldrh r1, [r3, #0] //R1 USB->CNTR
  714. movs r5, #0x08
  715. orrs r1, r5 //set FSUSP
  716. strh r1, [r3, #0] //USB->CNTR R2
  717. movs r1, #usbd_evt_susp
  718. movs r4, #ISTRBIT(11)
  719. b .L_ep_clristr
  720. /* do reset routine */
  721. .L_ep_resetm:
  722. movs r1, #7
  723. ldr r2, =#USB_EPBASE
  724. ldr r0, =#USB_PMABASE
  725. ldr r5, =#EP_NOTOG
  726. .L_ep_reset_loop:
  727. ldrh r4, [r2]
  728. bics r4, r5
  729. strh r4, [r2]
  730. movs r4, #0
  731. strh r4, [r0, #TXADDR]
  732. strh r4, [r0, #TXCOUNT]
  733. strh r4, [r0, #RXADDR]
  734. strh r4, [r0, #RXCOUNT]
  735. adds r2, #0x04
  736. adds r0, #0x10
  737. subs r1, #1
  738. bpl .L_ep_reset_loop
  739. movs r2, #0x00
  740. strh r2, [r3, #0x10] // 0 -> USB->BTABLE
  741. movs r1, #usbd_evt_reset
  742. movs r4, #ISTRBIT(10)
  743. .L_ep_clristr:
  744. lsls r4, #ISTRSHIFT
  745. ldrh r0, [r3, #4]
  746. bics r0, r4
  747. strh r0, [r3, #4]
  748. .L_ep_callback:
  749. pop {r0, r3, r4, r5 }
  750. bx r3
  751. .size _evt_poll, . - _evt_poll
  752. .pool
  753. .end
  754. #endif //USBD_STM32L100