usb_32v0A.S 21 KB

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  1. /* This file is the part of the LUS32 project
  2. *
  3. * Copyright ©2016 Dmitry Filimonchuk <dmitrystu[at]gmail[dot]com>
  4. *
  5. * Licensed under the Apache License, Version 2.0 (the "License");
  6. * you may not use this file except in compliance with the License.
  7. * You may obtain a copy of the License at
  8. * http://www.apache.org/licenses/LICENSE-2.0
  9. * Unless required by applicable law or agreed to in writing, software
  10. * distributed under the License is distributed on an "AS IS" BASIS,
  11. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. * See the License for the specific language governing permissions and
  13. * limitations under the License.
  14. */
  15. #if !defined (__ASSEMBLER__)
  16. #define __ASSEMBLER__
  17. #endif
  18. #include "../usb.h"
  19. #include "memmap.inc"
  20. #if defined(USE_STMV0A_DRIVER)
  21. #define EP_SETUP 0x0800
  22. #define EP_TYPE 0x0600
  23. #define EP_KIND 0x0100
  24. #define EP_ADDR 0x000F
  25. #define EP_RX_CTR 0x8000
  26. #define EP_RX_DTOG 0x4000
  27. #define EP_RX_STAT 0x3000
  28. #define EP_RX_SWBUF 0x0040
  29. #define EP_RX_DIS 0x0000
  30. #define EP_RX_STAL 0x1000
  31. #define EP_RX_NAK 0x2000
  32. #define EP_RX_VAL 0x3000
  33. #define EP_TX_CTR 0x0080
  34. #define EP_TX_DTOG 0x0040
  35. #define EP_TX_STAT 0x0030
  36. #define EP_TX_SWBUF 0x4000
  37. #define EP_TX_DIS 0x0000
  38. #define EP_TX_STAL 0x0010
  39. #define EP_TX_NAK 0x0020
  40. #define EP_TX_VAL 0x0030
  41. #define RXADDR0 0x00
  42. #define RXCOUNT0 0x02
  43. #define RXADDR1 0x04
  44. #define RXCOUNT1 0x08
  45. #define TXADDR0 0x00
  46. #define TXCOUNT0 0x02
  47. #define TXADDR1 0x04
  48. #define TXCOUNT1 0x08
  49. #define TXADDR 0x00
  50. #define TXCOUNT 0x02
  51. #define RXADDR 0x04
  52. #define RXCOUNT 0x08
  53. #define EP_NOTOG (EP_RX_CTR | EP_TX_CTR | EP_SETUP | EP_TYPE | EP_KIND | EP_ADDR)
  54. #define TGL_SET(mask, bits) ((EP_NOTOG | (mask))<<16 | (bits))
  55. #define TX_STALL TGL_SET(EP_TX_STAT, EP_TX_STAL)
  56. #define RX_STALL TGL_SET(EP_RX_STAT, EP_RX_STAL)
  57. #define TX_USTALL TGL_SET(EP_TX_STAT | EP_TX_DTOG, EP_TX_NAK)
  58. #define RX_USTALL TGL_SET(EP_RX_STAT | EP_RX_DTOG, EP_RX_VAL)
  59. #define DTX_USTALL TGL_SET(EP_TX_STAT | EP_TX_DTOG | EP_TX_SWBUF, EP_TX_VAL)
  60. #define DRX_USTALL TGL_SET(EP_RX_STAT | EP_RX_DTOG | EP_RX_SWBUF, EP_RX_VAL | EP_RX_SWBUF)
  61. .syntax unified
  62. .cpu cortex-m0plus
  63. .text
  64. .thumb
  65. .globl usb_stmv0a
  66. .align 2
  67. usb_stmv0a:
  68. .long _enable
  69. .long _reset
  70. .long _connect
  71. .long _setaddr
  72. .long _ep_config
  73. .long _ep_deconfig
  74. .long _ep_read
  75. .long _ep_write
  76. .long _ep_setstall
  77. .long _ep_isstalled
  78. .long _evt_poll
  79. .long _get_frame
  80. .long _get_serial_desc
  81. .size usb_stmv0a, . - usb_stmv0a
  82. .thumb_func
  83. .type _get_serial_desc, %function
  84. /* uint16_t get_serial_desc (void *buffer)
  85. * R0 <- buffer for the string descriptor
  86. * descrpitor size -> R0
  87. */
  88. _get_serial_desc:
  89. push {r4, r5, lr}
  90. movs r1,18 //descriptor size 18 bytes
  91. strb r1,[r0]
  92. movs r1, #0x03 //DTYPE_STRING
  93. strb r1,[r0, #0x01]
  94. ldr r5, .L_uid_base //UID3 this is the serial number
  95. ldr r4, .L_fnv1a_offset //FNV1A offset
  96. ldr r2, [r5, 0x00] //UID0
  97. bl .L_fnv1a
  98. ldr r2, [r5, 0x04] //UID1
  99. bl .L_fnv1a
  100. ldr r2, [r5, 0x14] //UID2
  101. bl .L_fnv1a
  102. movs r3, #28
  103. .L_gsn_loop:
  104. movs r1, r4
  105. lsrs r1, r3
  106. lsls r1, #28
  107. lsrs r1, #28
  108. adds r1, #0x30 //'0'
  109. cmp r1, #0x3A
  110. blo .L_gsn_store
  111. adds r1, #0x07 //'A' - '0'
  112. .L_gsn_store:
  113. adds r0, #0x02
  114. strb r1, [r0]
  115. lsrs r1, #0x08
  116. strb r1, [r0, #0x01]
  117. subs r3, #0x04
  118. bpl .L_gsn_loop
  119. movs r0, #18
  120. pop {r4, r5, pc}
  121. .L_fnv1a:
  122. movs r3, #0x04
  123. .L_fnv1a_loop:
  124. uxtb r1, r2
  125. eors r4, r1
  126. ldr r1, .L_fnv1a_prime //FNV1A prime
  127. muls r4, r1
  128. lsrs r2, #0x08
  129. subs r3, #0x01
  130. bne .L_fnv1a_loop
  131. bx lr
  132. .align 2
  133. .L_fnv1a_prime: .long 16777619
  134. .L_fnv1a_offset: .long 2166136261
  135. .L_uid_base: .long UID_BASE
  136. .size _get_serial_desc, . - _get_serial_desc
  137. .thumb_func
  138. .type _connect, %function
  139. _connect:
  140. subs r1, r0, #1
  141. sbcs r0, r1
  142. lsls r0, #15
  143. ldr r1, =#USB_REGBASE
  144. strh r0, [r1, #USB_BCDR] //USB->BCDR
  145. bx lr
  146. .size _connect, . - _connect
  147. .thumb_func
  148. .type _setaddr, %function
  149. _setaddr:
  150. ldr r1, =USB_REGBASE
  151. adds r0, #0x80
  152. strh r0, [r1, #USB_DADDR] //USB->DADDR
  153. bx lr
  154. .size _setaddr, . - _setaddr
  155. .thumb_func
  156. .type _reset, %function
  157. _reset:
  158. ldr r2, =#USB_REGBASE
  159. movs r0, #0x01 //FRES
  160. ldrh r1, [r2, #USB_CNTR] //USB->CNTR
  161. orrs r1, r0
  162. strh r1, [r2, #USB_CNTR] // set FRES
  163. bics r1, r0
  164. strh r1, [r2, #USB_CNTR] // clr FRES
  165. bx lr
  166. .size _reset, . - _reset
  167. .thumb_func
  168. .type _get_frame, %function
  169. _get_frame:
  170. ldr r0, =#USB_REGBASE
  171. ldrh r0, [r0, #USB_FNR] //FNR
  172. lsls r0, #21
  173. lsrs r0, #21
  174. bx lr
  175. .size _get_frame, . - _get_frame
  176. .thumb_func
  177. .type _enable, %function
  178. _enable:
  179. ldr r1, =#USB_REGBASE //USB->CNTR
  180. ldr r2, =#RCC_BASE //RCC
  181. movs r3, #0x01
  182. lsls r3, #23 //USBEN or USBRST
  183. tst r0, r0
  184. beq .L_disable
  185. .L_enable:
  186. ldr r0, [r2, #RCC_APB1ENR]
  187. orrs r0, r3
  188. str r0, [r2, #RCC_APB1ENR] //RCC->APB1ENR |= USBEN
  189. ldr r0, [r2, #RCC_APB1RSTR]
  190. orrs r0, r3
  191. str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR |= USBRST
  192. bics r0, r3
  193. str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR &= ~USBRST
  194. movs r0, #0xBE
  195. lsls r0, #0x08 // CTRM | ERRM | WKUPM | SUSPM | RESETM | SOFM
  196. strh r0, [r1] //set USB->CNTR
  197. bx lr
  198. .L_disable:
  199. ldr r0, [r2, #RCC_APB1ENR]
  200. tst r0, r3
  201. beq .L_enable_end // usb is disabled
  202. movs r0, #0x00
  203. strh r0, [r1, #USB_BCDR] //USB->BCDR disable USB I/O
  204. ldr r0, [r2, #RCC_APB1RSTR]
  205. orrs r0, r3
  206. str r0, [r2, #RCC_APB1RSTR] //RCC->APB1RSTR |= USBRST
  207. ldr r0, [r2, #RCC_APB1ENR]
  208. bics r0, r3
  209. str r0, [r2, #RCC_APB1ENR] //RCC->APB1ENR &= ~USBEN
  210. .L_enable_end:
  211. bx lr
  212. .size _enable, . - _enable
  213. .thumb_func
  214. .type _ep_setstall, %function
  215. /*void ep_settall(uint8_t ep, bool stall)
  216. * in R0 <- endpoint number
  217. * in R1 <- 0 if unstall, !0 if stall
  218. */
  219. _ep_setstall:
  220. lsls r2, r0, #28
  221. lsrs r2, #26
  222. ldr r3, =#USB_EPBASE
  223. adds r3, r2 // epr -> r3
  224. movs r2, 0x30 // TX_STAT_MASK -> r2
  225. cmp r0, #80
  226. blo .L_eps_rx
  227. .L_eps_tx:
  228. ldr r0, =#TX_STALL //stall TX
  229. tst r1, r1
  230. bne .L_eps_reg_set
  231. .L_eps_tx_unstall:
  232. ldrh r1, [r3] // *epr -> r1
  233. lsls r1, #21
  234. lsrs r1, #29 // EPTTYPE | EPKIND mask only
  235. ldr r0, =#DTX_USTALL //unstall dblbulk or iso TX (VALID and clr DTOG_TX & SWBUF_TX)
  236. cmp r1, #0x01 // if doublebuffered bulk endpoint
  237. beq .L_eps_reg_set
  238. cmp r1, #0x04 // if isochronous endpoint
  239. ldr r0, =#TX_USTALL // unstall other TX (NAKED + clr DTOG_TX)
  240. b .L_eps_reg_set
  241. .L_eps_rx:
  242. lsls r2, #8 // RX_STAT_MASK -> R2
  243. ldr r0,=#RX_STALL //stall RX
  244. tst r1, r1
  245. bne .L_eps_reg_set
  246. .L_eps_rx_unstall:
  247. ldrh r1, [r3] // *epr -> r1
  248. lsls r1, #21
  249. lsrs r1, #29 // EPTTYPE | EPKIND mask only
  250. ldr r0, =#DRX_USTALL //unstall dblbulk or iso (VALID. clr DTOG_RX set SWBUF_RX)
  251. cmp r1, #0x01 // if dblbulk
  252. beq .L_eps_reg_set
  253. cmp r1, #0x04 // if iso
  254. beq .L_eps_reg_set
  255. ldr r0, =#RX_USTALL // unstall other RX (VALID + clr
  256. /* R0 - mask and toggle bits
  257. * R2 - mask for STAT bits
  258. * R3 - endpoint register pointer
  259. */
  260. .L_eps_reg_set:
  261. ldrh r1, [r3] // *epr -> r1
  262. ands r2, r1 // check if endpoint disabled
  263. beq .L_eps_exit // do nothing
  264. eors r1, r0
  265. lsrs r0, #16
  266. ands r1, r0
  267. strh r1, [r3]
  268. .L_eps_exit:
  269. bx lr
  270. .size _ep_setstall, . - _ep_setstall
  271. .thumb_func
  272. .type _ep_isstalled, %function
  273. /* bool ep_isstalled(uint8t ep) */
  274. _ep_isstalled:
  275. ldr r1, =#USB_EPBASE
  276. lsls r2, r0, #28
  277. lsrs r2, #26
  278. ldr r1, [r1, r2]
  279. lsls r1, #17
  280. cmp r0, #0x80
  281. bhs .L_eis_check
  282. lsls r1, #8
  283. .L_eis_check:
  284. lsrs r1, r1, #28
  285. subs r1, #0x01
  286. subs r0, r1, #0x01
  287. sbcs r1, r1
  288. rsbs r0, r1, #0
  289. bx lr
  290. .size _ep_isstalled, . - _ep_isstalled
  291. .thumb_func
  292. .type _ep_read, %function
  293. /* uint16_t _ep_read(uint8_t ep, void *buf, uint16_t blen)
  294. * in R0 <- endpoint
  295. * in R1 <- *buffer
  296. * in R2 <- length of the buffer
  297. * out length of the recieved data -> R0
  298. */
  299. _ep_read:
  300. push {r4, r5, lr}
  301. ldr r3, =#USB_EPBASE
  302. ldr r4, =#USB_PMABASE
  303. lsls r0, #28
  304. lsrs r0, #26
  305. adds r3, r0 // *EPR -> R3
  306. lsls r0, #1
  307. adds r4, r0 // *EPT -> R4
  308. ldrh r0, [r3] // reading epr
  309. lsls r5, r0, #21
  310. lsrs r5, #29
  311. cmp r5, #0x04
  312. beq .L_epr_iso
  313. cmp r5, #0x01
  314. bne .L_epr_sngl
  315. .L_epr_dblbulk:
  316. negs r0, r0
  317. lsrs r0, #7 // ~SW_RX in CF
  318. b .L_epr_load_table
  319. .L_epr_iso:
  320. lsrs r0, #15 // DTOG_RX passsed to CF
  321. .L_epr_load_table:
  322. ldrh r0, [r4, #0] // R0 rxaddr0
  323. ldrh r5, [r4, #2] // R5 rxcnt0
  324. bcs .L_epr_prepare
  325. .L_epr_sngl:
  326. ldrh r0, [r4, #4] // R0 rxaddr1 or rxaddr
  327. ldrh r5, [r4, #6] // R5 rxcnt1 or rxcnt
  328. .L_epr_prepare:
  329. ldr r4, =#USB_PMABASE
  330. adds r0, r4 // R0 now has a physical address
  331. lsls r5, #22
  332. lsrs r5, #22 // R5 bytes count
  333. cmp r2, r5
  334. blo .L_epr_read
  335. mov r2, r5 // if buffer is larger
  336. .L_epr_read:
  337. cmp r2, #1
  338. blo .L_epr_read_end
  339. ldrh r4, [r0]
  340. strb r4, [r1]
  341. beq .L_epr_read_end
  342. lsrs r4, #8
  343. strb r4, [r1, #1]
  344. adds r1, #2
  345. adds r0, #2
  346. subs r2, #2
  347. bne .L_epr_read
  348. .L_epr_read_end:
  349. ldrh r0, [r3]
  350. lsls r1, r0, #21
  351. lsrs r1, #29
  352. cmp r1, #0x04
  353. beq .L_epr_exit // ep is iso. no needs to set it to valid
  354. cmp r1, #0x01
  355. beq .L_epr_exit // ep is dblbulk. no needs to set it to valid
  356. ldr r2, =#TGL_SET(EP_RX_STAT , EP_RX_VAL)
  357. eors r0, r2
  358. lsrs r2, #16
  359. ands r0, r2
  360. strh r0, [r3] // set ep to VALID state
  361. .L_epr_exit:
  362. mov r0, r5
  363. pop {r4, r5, pc}
  364. .size _ep_read, . - _ep_read
  365. .thumb_func
  366. .type _ep_write, %function
  367. /* uint16_t ep_write(uint8_t ep, void *buf, uint16_t blen)
  368. *
  369. */
  370. _ep_write:
  371. push {r2, r4, r5, lr}
  372. ldr r3, =#USB_EPBASE
  373. ldr r4, =#USB_PMABASE
  374. lsls r0, #28
  375. lsrs r0, #26
  376. adds r3, r0 // *EPR -> R3
  377. lsls r0, #1
  378. adds r4, r0 // *EPT -> R4
  379. ldrh r0, [r3] // reading epr
  380. lsls r0, #21
  381. lsrs r0, #29
  382. subs r0, #0x04
  383. beq .L_epw_iso
  384. adds r0, #0x03
  385. bne .L_epw_sngl
  386. .L_epw_dblbulk:
  387. ldrh r0, [r3]
  388. lsrs r0, #15 // SW_TX in CF
  389. bcc .L_epw_sngl
  390. b .L_epw_settx1
  391. .L_epw_iso:
  392. ldrh r0, [r3]
  393. lsrs r0, #7 // DTOG_TX passsed to CF
  394. bcs .L_epw_sngl
  395. .L_epw_settx1:
  396. adds r4, #0x04
  397. .L_epw_sngl:
  398. ldrh r0, [r4, #0] // R0 txaddr
  399. .L_epw_prepare:
  400. strh r2, [r4, #2] // set txcount
  401. ldr r4, =#USB_PMABASE
  402. adds r0, r4
  403. .L_epw_write:
  404. cmp r2, #0x01
  405. blo .L_epw_writeend
  406. ldrb r4, [r1]
  407. beq .L_epw_halfw
  408. ldrb r5, [r1, #1]
  409. lsls r5, #8
  410. orrs r4, r5
  411. strh r4, [r0]
  412. adds r1, #2
  413. adds r0, #2
  414. subs r2, #2
  415. b .L_epw_write
  416. .L_epw_halfw:
  417. strh r4, [r0]
  418. .L_epw_writeend:
  419. ldrh r0, [r3]
  420. lsls r1, r0, #21
  421. lsrs r1, #29
  422. cmp r1, #0x04
  423. beq .L_epw_exit //nothing to do with ISO ep
  424. ldr r2, =#TGL_SET(EP_TX_STAT, EP_TX_VAL)
  425. cmp r1, #0x01
  426. bne .L_epw_setstate
  427. // ep is dblbulk. needs to switch SW_TX
  428. ldr r2, =#TGL_SET(EP_TX_SWBUF, EP_TX_SWBUF)
  429. bics r0, r2 //clearing SW_BUF for setting in to 1 by XOR
  430. .L_epw_setstate:
  431. eors r0, r2
  432. lsrs r2, #16
  433. ands r0, r2
  434. strh r0, [r3]
  435. .L_epw_exit:
  436. pop {r0, r4, r5, pc}
  437. .size _ep_write, .- _ep_write
  438. /* internal function */
  439. /* requester size passed in R2 */
  440. /* result returns in R0 CF=1 if OK*/
  441. _get_next_pma:
  442. push {r1, r3, r4, lr}
  443. movs r1, #16
  444. movs r3, #1
  445. lsls r3, #10 //R3 MAX_PMA_SIZE
  446. ldr r0, =#USB_PMABASE
  447. .L_gnp_chkaddr:
  448. ldrh r4, [r0, #0] //addr
  449. tst r4, r4
  450. beq .L_gnp_nxtaddr
  451. cmp r3, r4
  452. blo .L_gnp_nxtaddr
  453. mov r3, r4
  454. .L_gnp_nxtaddr:
  455. adds r0, #4
  456. subs r1, #1
  457. bne .L_gnp_chkaddr
  458. subs r0, r3, r2
  459. blo .L_gnp_exit
  460. cmp r0, #0x40 //check for the pma table overlap
  461. .L_gnp_exit:
  462. pop {r1, r3, r4, pc}
  463. .size _get_next_pma, . - _get_next_pma
  464. .thumb_func
  465. .type _ep_config, %function
  466. /* bool ep_config(uint8_t ep, uint8_t eptype, uint16_t epsize)
  467. * R0 <- ep
  468. * R1 <- eptype
  469. * R2 <- epsize
  470. * result -> R0
  471. */
  472. _ep_config:
  473. push {r4, r5, lr}
  474. movs r3, 0x01
  475. ands r3, r2
  476. adds r2, r3 //R2 -> halfword aligned epsize
  477. movs r3, #0x00 //BULK
  478. cmp r1, #0x02 // is eptype bulk ?
  479. beq .L_epc_settype
  480. movs r3, #0x01 //DBLBULK
  481. cmp r1, #0x06
  482. beq .L_epc_settype
  483. movs r3, #0x02 //CONTROL
  484. cmp r1, #0x00
  485. beq .L_epc_settype
  486. movs r3, #0x04 //ISO
  487. cmp r1, #0x01
  488. beq .L_epc_settype
  489. movs r3, #0x06 //INTERRUPT
  490. .L_epc_settype:
  491. lsls r3, #8
  492. lsls r4, r0, #28
  493. lsrs r4, #28
  494. orrs r3, r4
  495. lsls r4, #2
  496. ldr r5, =#USB_EPBASE
  497. strh r3, [r5, r4] //setup EPTYPE EPKIND EPADDR
  498. cmp r1, #0x00 // is a control ep ?
  499. beq .L_epc_setuptx
  500. cmp r0, #0x80
  501. blo .L_epc_setuprx
  502. .L_epc_setuptx:
  503. ldr r5, =#USB_PMABASE
  504. lsls r4, #1
  505. adds r5, r4
  506. bl _get_next_pma
  507. bcc .L_epc_fail
  508. strh r0, [r5, #TXADDR] //store txaddr or txaddr0
  509. movs r0, #0x00
  510. strh r0, [r5, #TXCOUNT] //store txcnt
  511. cmp r1, #0x06 // is DBLBULK
  512. beq .L_epc_txdbl
  513. ldr r3, =#TX_USTALL //set state NAKED , clr DTOG_TX
  514. cmp r1, #0x01 // is ISO
  515. bne .L_epc_txsetstate //
  516. .L_epc_txdbl:
  517. ldr r3, =#DTX_USTALL //set state VALID clr DTOG_TX & SWBUF_TX
  518. bl _get_next_pma
  519. bcc .L_epc_fail
  520. strh r0, [r5, #TXADDR1] //store txaddr1
  521. movs r0, #0x00
  522. strh r0, [r5, #TXCOUNT1] //store txcnt
  523. .L_epc_txsetstate:
  524. ldr r5, =#USB_EPBASE
  525. lsrs r4, #1
  526. ldrh r0, [r5, r4]
  527. eors r0, r3
  528. lsrs r3, #16
  529. ands r0, r3
  530. strh r0, [r5, r4]
  531. cmp r1, #0x00 //is a control ep ?
  532. bne .L_epc_exit
  533. .L_epc_setuprx:
  534. mov r3, r2
  535. cmp r2, #62
  536. bls .L_epc_rxbb
  537. movs r3, #0x1F
  538. ands r3, r2
  539. bne .L_epc_rxaa
  540. subs r2, #0x20
  541. .L_epc_rxaa:
  542. bics r2, r3
  543. lsrs r3, r2, #4
  544. adds r3, #0x40
  545. adds r2, #0x20
  546. .L_epc_rxbb:
  547. lsls r3, #9
  548. ldr r5, =#USB_PMABASE
  549. lsls r4, #1
  550. adds r5, r4
  551. cmp r1, 0x06 //if dblbulk
  552. beq .L_epc_rxdbl
  553. cmp r1, 0x01 // iso
  554. bne .L_epc_rxsngl
  555. .L_epc_rxdbl:
  556. bl _get_next_pma
  557. bcc .L_epc_fail
  558. strh r0, [r5, #RXADDR0] //store rxaddr0
  559. strh r3, [r5, #RXCOUNT0] //store rxcnt0
  560. bl _get_next_pma
  561. bcc .L_epc_fail
  562. strh r0, [r5, #RXADDR1] //store rxaddr1
  563. strh r3, [r5, #RXCOUNT1] //store rxcnt1
  564. ldr r3, =#DRX_USTALL
  565. b .L_epc_rxsetstate
  566. .L_epc_rxsngl:
  567. bl _get_next_pma
  568. bcc .L_epc_fail
  569. strh r0, [r5, #RXADDR] //store rxaddr1 or rxaddr
  570. strh r3, [r5, #RXCOUNT] //store rxcnt1 or rxcnt
  571. ldr r3, =#RX_USTALL
  572. .L_epc_rxsetstate:
  573. ldr r5, =#USB_EPBASE
  574. lsrs r4, #1
  575. ldrh r0, [r5, r4]
  576. eors r0, r3
  577. lsrs r3, #16
  578. ands r0, r3
  579. strh r0, [r5, r4]
  580. .L_epc_exit:
  581. movs r0, #0x01
  582. pop {r4, r5, pc}
  583. .L_epc_fail:
  584. movs r0, #0x00
  585. pop {r4, r5, pc}
  586. .size _ep_config, . - _ep_config
  587. .thumb_func
  588. .type _ep_deconfig, %function
  589. /* void ep_deconfig( uint8_t ep)
  590. * R0 <- ep
  591. */
  592. _ep_deconfig:
  593. lsls r1, r0, #28
  594. lsrs r1, #26
  595. ldr r2, =#USB_EPBASE
  596. ldr r3, =#USB_PMABASE
  597. adds r2, r1
  598. lsls r1, #1
  599. adds r3, r1
  600. /* clearing endpoint register */
  601. ldr r1, =#EP_NOTOG
  602. ldrh r0, [r2]
  603. bics r0, r1
  604. strh r0, [r2]
  605. /* clearing PMA data */
  606. movs r0, #0x00
  607. strh r0, [r3, #TXADDR]
  608. strh r0, [r3, #TXCOUNT]
  609. strh r0, [r3, #RXADDR]
  610. strh r0, [r3, #RXCOUNT]
  611. bx lr
  612. .size _ep_deconfig, . - _ep_config
  613. #define ISTRSHIFT 8
  614. #define ISTRBIT(bit) ((1 << bit) >> ISTRSHIFT)
  615. .thumb_func
  616. .type _evt_poll, %function
  617. /*void evt_poll(usbd_device *dev, usbd_evt_callback callback)*/
  618. _evt_poll:
  619. push {r0, r1, r4, r5}
  620. ldr r3, =#USB_REGBASE
  621. ldrh r0, [r3, #4] //USB->ISTR -> R2
  622. /* ep_index -> R2 */
  623. movs r2, 0x07
  624. ands r2, r0
  625. /* checking USB->ISTR for events */
  626. lsls r0, #17 //CTRM -> CF
  627. bcs .L_ep_ctrm
  628. lsls r0, #2 //ERRM -> CF
  629. bcs .L_ep_errm
  630. lsls r0, #1 //WKUPM -> CF
  631. bcs .L_ep_wkupm
  632. lsls r0, #1 //SUSPM -> CF
  633. bcs .L_ep_suspm
  634. lsls r0, #1 //RESETM -> CF
  635. bcs .L_ep_resetm
  636. lsls r0, #1 //SOFM -> CF
  637. bcs .L_ep_sofm
  638. lsls r0, #1
  639. bcs .L_ep_esofm
  640. /* exit with no callback */
  641. pop {r0, r1, r4 , r5}
  642. bx lr
  643. .L_ep_ctrm:
  644. movs r3, #0x00
  645. ldr r0,=#USB_EPBASE
  646. lsrs r0, #2
  647. adds r0, r2
  648. lsls r0, #2 // R0 ep register address
  649. ldrh r4, [r0] //R4 *USB->EPx
  650. lsrs r5, r4, #8 // CTR_TX -> CF
  651. bcc .L_ep_ctr_rx
  652. /* CTR_TX event */
  653. movs r1, #usbd_evt_eptx
  654. movs r5, #0x80
  655. adds r2, #0x80 // set endpoint tx
  656. b .L_ep_clr_ctr
  657. .L_ep_ctr_rx:
  658. /* CTR_RX RX or SETUP */
  659. movs r1, #usbd_evt_epsetup
  660. lsls r5, r4, #21 //SETUP -> CF
  661. bcs .L_ep_ctr_evt
  662. movs r1, #usbd_evt_eprx
  663. lsrs r5, #29 //EP_TYPE | EP_KIND -> R5 LSB
  664. cmp r5, #0x01 //if dblbuf bulk
  665. bne .L_ep_ctr_evt
  666. /* if ep is dblbulk RX */
  667. movs r3, #EP_RX_SWBUF
  668. .L_ep_ctr_evt:
  669. /* clear CTR_RX */
  670. movs r5, #0x80
  671. lsls r5, #0x08
  672. .L_ep_clr_ctr:
  673. bics r4, r5
  674. ldr r5, =#EP_NOTOG
  675. ands r4, r5
  676. orrs r4, r3
  677. strh r4, [r0] // clr CTR flag
  678. b .L_ep_callback
  679. .L_ep_errm:
  680. movs r1, #usbd_evt_error
  681. movs r4, #ISTRBIT(13)
  682. b .L_ep_clristr
  683. .L_ep_sofm:
  684. movs r1, #usbd_evt_sof
  685. movs r4, #ISTRBIT(9)
  686. b .L_ep_clristr
  687. .L_ep_esofm:
  688. movs r1, #usbd_evt_esof
  689. movs r4, #ISTRBIT(8)
  690. b .L_ep_clristr
  691. .L_ep_wkupm:
  692. ldrh r1, [r3, #0] //R1 USB->CNTR
  693. movs r5, #0x08
  694. bics r1, r5 //clr FSUSP
  695. strh r1, [r3, #0] //USB->CNTR R2
  696. movs r1, #usbd_evt_wkup
  697. movs r4, #ISTRBIT(12)
  698. b .L_ep_clristr
  699. .L_ep_suspm:
  700. ldrh r1, [r3, #USB_CNTR] //R1 USB->CNTR
  701. movs r5, #0x08
  702. orrs r1, r5 //set FSUSP
  703. strh r1, [r3, #USB_CNTR] //USB->CNTR R2
  704. movs r1, #usbd_evt_susp
  705. movs r4, #ISTRBIT(11)
  706. b .L_ep_clristr
  707. /* do reset routine */
  708. .L_ep_resetm:
  709. movs r1, #7
  710. ldr r2, =#USB_EPBASE
  711. ldr r0, =#USB_PMABASE
  712. ldr r5, =#EP_NOTOG
  713. .L_ep_reset_loop:
  714. ldrh r4, [r2]
  715. bics r4, r5
  716. strh r4, [r2]
  717. movs r4, #0
  718. strh r4, [r0, #TXADDR]
  719. strh r4, [r0, #TXCOUNT]
  720. strh r4, [r0, #RXADDR]
  721. strh r4, [r0, #RXCOUNT]
  722. adds r2, #4
  723. adds r0, #8
  724. subs r1, #1
  725. bpl .L_ep_reset_loop
  726. movs r2, #0x00
  727. strh r2, [r3, #USB_BTABLE] // 0 -> USB->BTABLE
  728. movs r1, #usbd_evt_reset
  729. movs r4, #ISTRBIT(10)
  730. .L_ep_clristr:
  731. lsls r4, #ISTRSHIFT
  732. ldrh r0, [r3, #4]
  733. bics r0, r4
  734. strh r0, [r3, #4]
  735. .L_ep_callback:
  736. pop {r0, r3, r4, r5 }
  737. bx r3
  738. .size _evt_poll, . - _evt_poll
  739. .pool
  740. .end
  741. #endif